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<reg[3] for special meaning.> <I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2.> #105

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<reg[3] for special meaning.> <I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2.> #105

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@zhaoleicpp
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reg[3] for special meaning.
not documented.
But I tested. It works fine.

@dlbeer
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dlbeer commented Jun 8, 2021 via email

@zhaoleicpp zhaoleicpp changed the title reg[3] for special meaning. reg[3] for special meaning. I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: 0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst 0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst 0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst 0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst when src is reg[3], it has special meanings. According to the oper, the Rsrc is Oper Rsrc MOVA 0 CMPA 0 ADDA 2 SUBA 2 Jun 17, 2021
@zhaoleicpp zhaoleicpp changed the title reg[3] for special meaning. I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: 0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst 0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst 0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst 0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst when src is reg[3], it has special meanings. According to the oper, the Rsrc is Oper Rsrc MOVA 0 CMPA 0 ADDA 2 SUBA 2 reg[3] for special meaning.\n I new a project using IAR, \n and debug it with the IAR simulator.\n I modified the instruction byte code,\n and get strange assembles that are not documented.\n I draw a conclusion in my opinion, \n for the following instructions: \n 0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst\n 0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst\n 0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst\n 0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst\n when src is reg[3], it has special meanings.\n According to the oper, the Rsrc is\n Oper Rsrc\n MOVA 0\n CMPA 0\n ADDA 2\n SUBA 2\n Jun 17, 2021
@zhaoleicpp zhaoleicpp changed the title reg[3] for special meaning.\n I new a project using IAR, \n and debug it with the IAR simulator.\n I modified the instruction byte code,\n and get strange assembles that are not documented.\n I draw a conclusion in my opinion, \n for the following instructions: \n 0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst\n 0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst\n 0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst\n 0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst\n when src is reg[3], it has special meanings.\n According to the oper, the Rsrc is\n Oper Rsrc\n MOVA 0\n CMPA 0\n ADDA 2\n SUBA 2\n reg[3] for special meaning. I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2. Jun 17, 2021
@dlbeer
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dlbeer commented Aug 15, 2021

Hi Zhao,

Sorry, I didn't get a notification when you'd changed the message, so I didn't notice that you'd done it!

The explanation is good, but if you could format the message in the standard style:

<short message>

<longer description ...>

Then it'll still be readable in the commit log. If you post a comment here when it's ready I'll merge it.

I've had a look through your other issues too -- it looks like you're making use of the simulator and know what you're doing. If you have any fixes for the issues you've found I'll be happy to accept those too.

Thanks,
Daniel

@zhaoleicpp
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Hi Zhao,

Sorry, I didn't get a notification when you'd changed the message, so I didn't notice that you'd done it!

The explanation is good, but if you could format the message in the standard style:

<short message>

<longer description ...>

Then it'll still be readable in the commit log. If you post a comment here when it's ready I'll merge it.

I've had a look through your other issues too -- it looks like you're making use of the simulator and know what you're doing. If you have any fixes for the issues you've found I'll be happy to accept those too.

Thanks,
Daniel

I just modify the code temporarily, I fill provide the issues later. The simulator does not give right result yet. I will fix the last bug witch is hard to find although. The bug location need automation, or I will be sleepy when I search them manually.

@zhaoleicpp zhaoleicpp changed the title reg[3] for special meaning. I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2. <reg[3] for special meaning.> <I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2.> Aug 21, 2021
@zhaoleicpp
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Iar_controller_to_debug_msp430_simulator.zip

To debug a simulator, I think automation is important. Here is Visual C++ code to control Iar.
Comparing Iar simulator and dlbeer mspdebug simulator step by step, every asm instruction, I　find the bug easily. Comparing registers and memory every instruction may be slow.
Unfortunate I believe the Iar simulator also has bugs.
I have no hardware and planning buy an MSP430F5529 develop board and a usb-debug-interface to continue debug work.
Hope the code may be helpful to you.

Best regards!

@dlbeer
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dlbeer commented Aug 24, 2021

Ok, thank you for your work on this. If you let me know when you think you have something ready, I'll merge. Let me know if you need any information from me in the meantime.

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