This is a repository of the Verilog Pre-Labs for EECS2021, a course taught at York University, Toronto, Canada.
Many students and I this term (Fall 2021) have struggled to complete the pre-labs, as they are mandatory self-learning and answers to these exercises are NOT provided by the instructors. The TAs are also not helpful enough; they are often too swamped with trying to help with the actual weekly lab content, which is not entirely related to the pre-lab content. These pre-labs are extremely time consuming and many students simply don't have the time to troubleshoot all these codes.
Thus, I am providing my completed versions of the pre-labs with the hope that others can benefit from the struggles that I and my fellow classmates had to go through to determine how to make this work. Credit has been given to co-authors in comments.
Warning: by reading any code from this repository, you agree that you peruse at your own risk.
Previous GitHubs published for this course were for a version of the course that used MIPS as the ISA. However, the course has been taught using the RISC-V instruction set since around 2017; thus, the code provided in those older GitHubs are not a 1:1 resource that can be used by current students.
The corresponding pre-lab handouts can be publicly found at this page: https://www.eecs.yorku.ca/teaching/docs/2021/
The prelabs for Verilog are K, L, M, and N.
As well, labs M and N require the Sequential Component Library which I have not included (as I did not author any part of them).
Link: https://www.eecs.yorku.ca/teaching/docs/2021/hrLib.zip
Lab M: I have included the ram.dat file, which I created using the RISC-V assembly file that I also included. You have to compile the RISC-V program in RVS, and then convert the binary representation into hexadecimal (I used a binary-to-hex converter online).
Lab N: The result of LabN2 and LabN3 are combined because I felt that yC1 and yC2 are too closely related to split up testing them.
NOTE: I will not be uploading codes for the RISC-V prelabs (A, B, C, D) because these pre-labs did not require students to figure out what the right code is; all the answers were already provided on the handouts. As well, those prelabs were less tedious - you could spend one evening to go through one handout and understand it quite well, whereas the Verilog labs needed at least 3 days worth of troubleshooting per handout.
For RISC-V you might find this tool useful: https://devin-lo.github.io/riscv_util.html
As well, I will NOT provide any additional resources for the EECS2021 course. Please do not solicit additional answers that I did not provide here.
Word of advice: Verilog is a C-like language. It may help you to take EECS2031 concurrently, or before taking this course.
This GitHub is published under the GNU General Public License v3.0