HLV/HSV flushes pipeline

[yuxuanliuuu]

In the Rocket-chip h-extension, HLV/HSV instructions flush pipeline every time. It requires 5 or 6 cycles to finish HLV/HSV instruction.
So the question is:
Is it necessary to flush the pipeline for instruction HLV/HSV?
Is it possible to prevent flushing the pipeline and how to do that?

[psherman42]

Maybe unrelated or specific chip idiosyncracy, but pipeline flush also occurs on, for example, when a series of amoxor.w instructions are rapidly executed and those instructions specify register x0 for their rd. Specifying any othr register (e.g., x1..x31) for rd produce write hazards and, thus, no pipeline flush for repeated invocations of amoxor.w.

Maybe something to think about for x0 (zero), atomics, and the pipeline?

See github repo psherman42/Understanding-AMO for more description and observation.