assembly tests passed to vcs

[YoussefZakari]

https://github.com/chipsalliance/rocket-chip/blob/v1.6/vsim/Makefrag-verilog

**cd$(sim_dir) && $(exec_simv) +permissive +max-cycles=$(timeout_cycles) +permissive-off $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]

after run will be something like this

cd . && ./simv-freechips.rocketchip.system-DefaultConfig +permissive -q +ntb_random_seed_automatic +permissive-off +permissive +verbose +max-cycles=100000000 +permissive-off output/rv64mi-p-scall 2> output/rv64mi-p-scall.out && [ $PIPESTATUS -eq 0 ]
mkdir -p ./output

I just want to know how output/rv64mi-p-scall is passed to the testbench and from where it is read inside the testbench/csrcs?