Question about riscv-tests and asm-test

[ZhaoHaowenn]

I'm trying to understand how Rocket-chip uses riscv-tests to test instruction sets. "*. S" uses RVTEST_PASS and RVTEST_FAIL to indicate whether the test was successful. But I'm confused about the execution details of these two macros. How rocket-chip testbench(Testdriver) monitor the test result through these two macro?
I wrote a simpler testbench and want to replace the original one using vcs, how can I monitor the results of the asm test?
related code:
https://github.com/riscv/riscv-test-env/blob/4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46/p/riscv_test.h#L247

[ZenithalHourlyRate]

How rocket-chip testbench(Testdriver) monitor the test result through these two macro?

This is done via an interface called Host-Target Interface (HTIF). It is implemented in rocket-chip, spike, pk, riscv-tests and many others so it is the de facto standard.

ucb-bar/riscv-sodor#13 (comment) said it should disappear soon. But AFAIK the only equivalent thing is semihosting and I think the semihosting spec is far from mature.

Besides these spec stuffs, the summary of the HTIF is that, with a .tohost section inside the elf, the loader (riscv-fesrv) of the elf (e.g. inside the vcs emulator) will know where to monitor, and once the software write something to .tohost, fesrv will know it and do something accordingly (e.g. exit(0), which means the test passed)

Specifically, for rocket-chip, in emulator.cc, the elf will be loaded by dtm_t, which has a DPI interface (see SimDTM.v) to the Debug Module RTL, to the main memory using Debug Module.

rocket-chip/src/main/resources/csrc/emulator.cc

Line 270 in 0ecf506

dtm = new dtm_t(htif_argc, htif_argv);

Then dtm_t will monitor the .tohost section inside the main memory with debug module, and once it finds exit(0), dtm->done() will become true and everything is fine now.

rocket-chip/src/main/resources/csrc/emulator.cc

Line 284 in 0ecf506

if (done_reset && (dtm->done() || jtag->done() || tile->io_success))

related code: https://github.com/riscv/riscv-test-env/blob/4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46/p/riscv_test.h#L247

As for this, the ecall interface is a generic interface. If you are baremetal, then see

https://github.com/riscv/riscv-test-env/blob/4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46/p/riscv_test.h#L178-L188

Which will directly write to tohost.

As for virtual memory, things are handled in pk and it will eventually become some tohost stuff