how to remove debug module SimDTM

[ZhaoHaowenn]

What should I do to get Testharness without SimDTM more conveniently? I found the answer "case DebugModuleKey = > None" in some issues, but I'm confused about details. Which file should I modify?
And I want to know how to get pure ExampleRocketSystem verilog file. Can anyone help on this?

[ZenithalHourlyRate]

Which file should I modify?

You might create a config that overrides that key, for example, in subsystem/Config.scala

class WithoutDebug extends Config ((site, here, up) => {
  case DebugModuleKey => None
})

and then apply it in system/Configs.scala to the default config

And I want to know how to get pure ExampleRocketSystem verilog file. Can anyone help on this?

That will depend on which branch of rocket-chip you are using. For dev branch it now emits a bunch of systemverilog file in out/emulator/freechips.rocketchip.system.TestHarness/freechips.rocketchip.system.DefaultConfig/firtool.dest if you have run through mill -i "emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig].elf"

If you are in master branch or releases you may run make verilog in emulator or vsim folder and find the generated verilog in generated-src/

[ZhaoHaowenn]

Appreciate your reply. For the second question, what I want to know is how to get output file without SimAXImem. In generated-src/ the freechips.rocketchip.system.xxx.v has SimAXImem connected to examplerocketsystem submodule. I can delete it manually but wonder how can I modify the chisel code to do it?

[ZenithalHourlyRate]

For the sbt flow, the following command might work but I have not verified it yet.

make verilog MODEL=ExampleRocketSystem

For the mill flow,

mill rocketchip -td dst -T freechips.rocketchip.system.ExampleRocketSystem -C freechips.rocketchip.system.DefaultConfig

which will generate a .fir in folder dst, then you can use firrtl (Maybe you need to went through the Makefile to find out how to use firrtl) to convert it to verilog.

rocket-chip/Makefrag

Line 37 in 25e2c63

FIRRTL ?= $(JAVA) -cp $(ROCKET_CHIP_JAR) firrtl.stage.FirrtlMain

rocket-chip/emulator/Makefrag-verilator

Lines 15 to 25 in 25e2c63

	%.v %.conf: %.fir $(ROCKET_CHIP_JAR)
	mkdir -p $(dir $@)
	$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) \
	-o $*.v \
	-X verilog \
	--infer-rw $(MODEL) \
	--repl-seq-mem -c:$(MODEL):-o:$*.conf \
	-faf $*.anno.json \
	-td $(generated_dir)/$(long_name)/ \
	-fct $(subst $(SPACE),$(COMMA),$(FIRRTL_TRANSFORMS)) \
	$(FIRRTL_OPTIONS) \

rocketchip jar can be generated in mill flow in this way.

$ mill rocketchip.assembly
[140/140] rocketchip.assembly 

$ ls out/rocketchip/assembly.dest/out.jar 

[ZhaoHaowenn]

The sbt flow works fine. Thanks.