Timing get worse ???

[IC-Dream]

Hi,

I synthesized the rocket core based on 28nm processing and also substituted the behavior SRAMs with the vendor-specific SRAMs, got the following timing report:

Critical Path:

That's is to say, the rocket core could run at most 500Mhz. Compared to the official data(page 15), there is a big gap. According to the official data, Based on 40nm processing, the rocket core could run over 1Ghz.

https://www.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.25-Tuesday-Epub/HC27.25.70-Processors-Epub/HC27.25.731-RISC-V-Lee-UCB-V4.with-backup.pdf

Why does the timing get worse ? or Have you did some specific optimization, but didn't release on github?

Any help will be appreciated.

[edcote]

Did you apply retiming to the FPU?

[IC-Dream]

I checked the generated verilog, for FMAC, it directly use the "*" operator, Doesn't the rocket generator implement the FMAC?

Thanks
Dream

[csgxiong]

Does Anyone have some idea about this ?

THANKS

[csgxiong]

We can add a multi-pipeline to FMAC.

[DecodeTheEncoded]

@IC-Dream do you have any update on this?