Skip to content

Issues: chipsalliance/fpga-interchange-schema

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

18 Open 9 Closed
18 Open 9 Closed
Author
Filter by author
Label
Filter by label
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Milestones
Filter by milestone
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Add Bel pins clocking information
#66 opened Oct 25, 2021 by acomodi
1
PinDelay should use StringIdx for bel pins, not BelPinIdx
#61 opened Jul 19, 2021 by gatecat
Get Conns for Wires
#60 opened Jul 16, 2021 by reillymck
Choice of bel pins for a cell pin
#55 opened May 18, 2021 by gatecat
1
"Inverting routing BELs" duplicated duplicate This issue or pull request already exists
#53 opened May 12, 2021 by mithro
Multi-output routing bels
#48 opened Apr 30, 2021 by gatecat
Site PIPs with side effects
#47 opened Apr 28, 2021 by gatecat
4
Inconsistent use of Text vs StringIdx
#46 opened Apr 27, 2021 by gatecat
5
Macro (and similar) placement constraints bug Something isn't working question Further information is requested
#44 opened Apr 26, 2021 by gatecat
2
Add badges to the README.
#37 opened Apr 16, 2021 by mithro
UltraScale clock routing documentation Improvements or additions to documentation question Further information is requested
#34 opened Apr 14, 2021 by gatecat
Expensive wire to node mapping
#32 opened Apr 13, 2021 by acomodi
1
Need simple MUX2 descriptions in device resources enhancement New feature or request help wanted Extra attention is needed
#29 opened Apr 8, 2021 by litghost
1
Parameter to tag mapping
#23 opened Mar 31, 2021 by gatecat
Need to add Read the Docs build and initial documentation structure documentation Improvements or additions to documentation good first issue Good for newcomers
#16 opened Feb 25, 2021 by litghost
Need to define timing model data schema
#15 opened Feb 25, 2021 by litghost
1
Inverter cell type
#14 opened Feb 25, 2021 by gatecat
Bus indices should (arguably) be signed not unsigned
#11 opened Feb 24, 2021 by gatecat
1
ProTip! Mix and match filters to narrow down what you’re looking for.