add yosys-plugins #645
add yosys-plugins #645
Conversation
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
… inference Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Rectified cells_sim & dsp_map files
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
…-tdp-inference ql-qlf: qlf_k6n10f: add TDP_BRAM36 inference
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…rence Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Equivalence checks for qlf_k6n10f DSP tests
Added installation of k6n10f simulation models that were missing
…dsp_simd pass class. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Removed const IdString class members
Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
update adder techmap
This works as an alias to 'read_verilog_with_uhdm' Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
…_alias Add 'read_systemverilog' command
…orce-parse Force -parse flag for Surelog when reading Verilog directly
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Remove unused modules from top_nodes
The code for handling unions has been added together with the code for structs, however it was never called due to a missing switch entry. Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
systemverilog: simplify unions
…cal-empty-string-test Use a canonical way to test for an empty string.
…dths Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
… widths Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
…-asymmetric-ram ql-qlf: k6n10f: add asymmetric RAM inference
[k6n10f] Preserve manually inserted DSPs
… name. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…ing. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…bram-inference Fix QuickLogic asymmetric BRAM inference
Instead of `which`, the suggested alternative is `command -v` Signed-off-by: Henner Zeller <h.zeller@acm.org>
…-which Fix deprecated use of `which`
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
umarcor
added
Dependencies
|
Why? |
|
@mithro to reduce the maintenance burden (CI, docs, etc.) and to reduce the fragmentation in the community (less experienced users not knowing where to report issues -f4pga, examples, plugins, conda, tools-). Nevertheless, this is likely to be kept on hold for a long time. |
|
This is over 78k lines of code, which is way more than all the code we have here at the moment. I'm all for unification of tools used in our toolchain under the f4pga python tool, but for now I think this might be a step too far, especially given that the yosys plugins are a standalone thing now and I think it makes sense to keep them that way. That being said, I don't know what every single one does. SystemVerilog parser is a plugin that a has a very general usage, that's not necessarily tied to f4pga flow, but maybe there's something else that is very specific to f4pga flow. I can't tell at the moment, but maybe in that case a better approach would be to bring those individual plugins that are very specific to our flow, here in separate PRs. |
|
@kboronski-ant, this PR is unrelated to the f4pga python tool. The reasoning is simpler:
Both the f4pga python tool and the plugins can be installed and used without cloning the repos, hence having them in the same location produces no conflict from a usage perspective. Nonetheless, as commented, this is to be kept on hold for a long time, because several other pending tasks need to be solved first. |
|
@umarcor - See chipsalliance/yosys-f4pga-plugins#312 -- we have been meaning to rename the repository because these they are not only useful for f4pga but ASIC people too. |
This PR moves the content of chipsalliance/yosys-f4pga-plugins to this repo as subdir
yosys-plugins.