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This is the code I write for my masters thesis. It will be an hopefully efficient implementation of quasicyclic LDPC codes for FPGAs. The hardware is written in VHDL and there also is a python implementation of the algorithms used. These were written to aid my understanding of the algorithms. Some of the VHDL is generated using python for a specific parity check matrix (H).

Name		Name	Last commit message	Last commit date
Latest commit History 121 Commits
vhdl		vhdl
.gitignore		.gitignore
README		README
README.md		README.md
ahhhrg.zip		ahhhrg.zip
codec_test.py		codec_test.py
conv_res.py		conv_res.py
decode.py		decode.py
decoder_base_gen.py		decoder_base_gen.py
decoder_soft_base_gen.py		decoder_soft_base_gen.py
encode.py		encode.py
encoder_fast_gen.py		encoder_fast_gen.py
encoder_gen.py		encoder_gen.py
greedy_alg_a.py		greedy_alg_a.py
qc_decoder_gen.py		qc_decoder_gen.py
qc_encode.py		qc_encode.py
test.txt		test.txt
test_mat.npy		test_mat.npy
vhdl.py		vhdl.py
workspace.zip		workspace.zip

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