A simulator for RISC-V instruction sets
Forked due to the fact branch history does not allow pull requests.
The simulator accepts binary files that contain RISC-V 32-bit instructions. The simulator should accept RV64I (integer) and RV64M (multiplication) instructions with the exception of instructions that take words as arguments (as they would require 64-bit instructions). These instructions may operate on 2001-byte memory - its size can be changed in Memory.java file.
This project has been a student project for course Computer Architecture and Engineering at DTU (Danmarks Tekniske Universitet). The project has been prepared together with Chennex, who is listed as source of this fork.