Add support for 32-bit RISC-V

[josecm]

This PR introduces support for RV32. Because the way the instruction set is written the difference is not much when comparing to RV64. The main areas of modification are:

• modifying assembly instructions that used 64-bit load/store directly by the LOAD/STORE macro which translates to either ld/st or lw/sw depending on if we are targetting RV64 or RV32, respectively;
• support for the sv32 translation mode. This also requires adapting the boot code where the bootstrap page-tables are built manually.
• adapt CSR access to CSRs that have a H variant (e.g., henvcfg, henvcfgh), and other small related issues;
• fix small issues that assumed 64-bit literals.

The PR also includes support for qemu-system-riscv32 virt machine, which is essentially a wrapper over the 64-bit variant.

The main issue with this port is related to the fact that we are required to map all available physical memory to perform page-table walks. Because the address space is so small (4GiB), this might not be possible as for RV64 we simply identity map all physical memory and assume these addresses won't collide with the high virtual addresses used by the hypervisor. This is not the case and we might not be able to map all physical addresses, which already happens for qemu-riscv32-virt if we configure it with memory larger than 1 GiB, since it starts memory at 0x80000000. We might need a dynamic mechanism similar to Linux's "highmem" in the future. I only think this is worth it if a real platform that requires it becomes available. Also, the main purpose of supporting RV32 is to target future MMU-less systems.

Test guest:

• Baremetal app
• Linux

Depends on #115