Sparse Matrix Multiplication Coprocessor

A sparse matrix multiplication FPGA architecture which acts as a 'coprocessor'.

Authors

University of the Pacific, Department of Electrical and Computer Engineering

Cody Balos, Crystal Beltran-Sanchez, Kelvin Hu

References

[1] Jamro, E., Pabiś, T., Russek, P., Wiatr, K.: The Algorithms for FPGA Implementation of Sparse Matrices Multiplication. Comput. Inform.

About

Created as Fall 2017 ECPE 194 (Advanced Digital Design) finalproject.