- I’m currently working on Embedded Systems, Digital Hardware Design & Verification
- 🔭 I’m currently working more with C++ and SystemVerilog
- 📫 How to reach me: andre.escariao1@gmail.com
Embedded Systems | RTL Design & Verification | UVM | Undergraduate in Electrical Engineering (UFCG)
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Universidade Federal de Campina Grande
- Campina Grande, Praíba, Brasil
- in/andreemedeiros
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SystemVerilog
SystemVerilog PublicSoluções do curso: Introduction to System Verilog - Siemens.
SystemVerilog 1
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