util_axis_fifo_asym: Initial testbench commit

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

util_axis_fifo_asym/Makefile

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+####################################################################################
+####################################################################################
+## Copyright 2022(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# All test-bench dependencies except test programs
+SV_DEPS += ../common/sv/utils.svh
+SV_DEPS += ../common/sv/logger_pkg.sv
+SV_DEPS += ../common/sv/reg_accessor.sv
+SV_DEPS += ../common/sv/m_axis_sequencer.sv
+SV_DEPS += ../common/sv/s_axis_sequencer.sv
+SV_DEPS += ../common/sv/m_axi_sequencer.sv
+SV_DEPS += ../common/sv/s_axi_sequencer.sv
+SV_DEPS += ../common/sv/test_harness_env.sv
+SV_DEPS += ../common/sv/adi_peripheral_pkg.sv
+SV_DEPS += ../common/sv/adi_regmap_pkg.sv
+SV_DEPS += ../common/sv/mailbox.sv
+SV_DEPS += ../common/sv/x_monitor.sv
+SV_DEPS += ../common/sv/scoreboard.sv
+SV_DEPS += ../common/sv/interfaces.svh
+SV_DEPS += environment.sv
+SV_DEPS += system_tb.sv
+
+ENV_DEPS += system_project.tcl
+ENV_DEPS += system_bd.tcl
+ENV_DEPS +=../scripts/adi_sim.tcl
+ENV_DEPS +=../scripts/run_sim.tcl
+
+LIB_DEPS := util_cdc
+LIB_DEPS += util_axis_fifo
+LIB_DEPS += util_axis_fifo_asym
+
+# default test program
+TP := test_program
+
+# config files should have the following format
+#  cfg_<param1>_<param2>.tcl
+CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
+#$(warning $(CFG_FILES))
+
+# List of tests and configuration combinations that has to be run
+# Format is:  <configuration>:<test name>
+TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
+#TESTS += cfg1_mm2mm_default:directed_test
+#TESTS += cfg1:test_program
+#TESTS += cfg2_fsync:test_program
+#TESTS += cfg2_fsync:test_frame_delay
+
+include ../scripts/project-sim.mk
+
+# usage :
+#
+# run specific test on a specific configuration in gui mode
+# 	make CFG=cfg2_fsync TST=test_frame_delay MODE=gui
+#
+# run all test from a configuration
+# 	make cfg1_mm2mm_default
+
+####################################################################################
+####################################################################################

util_axis_fifo_asym/README.md

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+Usage :
+
+Run all tests in batch mode:
+
+	make
+
+
+Run all tests in GUI mode:
+
+	make MODE=gui
+
+
+Run specific test on a specific configuration in gui mode:
+
+	make CFG=<name of cfg> TST=<name of test> MODE=gui
+
+
+Run all test from a configuration:
+
+	make <name of cfg>
+
+
+Where:
+
+ * <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
+ * <name of test> is a file from the tests directory without the tcl extension
+

util_axis_fifo_asym/cfgs/cfg1.tcl

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+global ad_project_params
+
+set random_width [expr int(8*pow(2, int(7.0*rand()+1)))]
+set ad_project_params(INPUT_WIDTH) $random_width
+
+set random_width [expr int(8*pow(2, int(7.0*rand()+1)))]
+set ad_project_params(OUTPUT_WIDTH) $random_width

util_axis_fifo_asym/environment.sv

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+`include "utils.svh"
+
+package environment_pkg;
+
+  import m_axi_sequencer_pkg::*;
+  import s_axi_sequencer_pkg::*;
+  import m_axis_sequencer_pkg::*;
+  import s_axis_sequencer_pkg::*;
+  import logger_pkg::*;
+
+  import axi_vip_pkg::*;
+  import axi4stream_vip_pkg::*;
+  import test_harness_env_pkg::*;
+  import scoreboard_pkg::*;
+  import x_monitor_pkg::*;
+
+  import `PKGIFY(test_harness, mng_axi_vip)::*;
+  import `PKGIFY(test_harness, ddr_axi_vip)::*;
+
+  import `PKGIFY(test_harness, input_axis)::*;
+  import `PKGIFY(test_harness, output_axis)::*;
+
+  class environment extends test_harness_env;
+
+    virtual interface clk_if input_clk_if;
+    virtual interface clk_if output_clk_if;
+
+    // agents and sequencers
+    `AGENT(test_harness, input_axis, mst_t) input_axis_agent;
+    `AGENT(test_harness, output_axis, slv_t) output_axis_agent;
+
+    m_axis_sequencer #(`AGENT(test_harness, input_axis, mst_t),
+                      `AXIS_VIP_PARAMS(test_harness, input_axis)
+                      ) input_axis_seq;
+    s_axis_sequencer #(`AGENT(test_harness, output_axis, slv_t)) output_axis_seq;
+
+    x_axis_monitor #(`AGENT(test_harness, input_axis, mst_t)) input_axis_mon;
+    x_axis_monitor #(`AGENT(test_harness, output_axis, slv_t)) output_axis_mon;
+
+    scoreboard scoreboard_inst;
+
+    //============================================================================
+    // Constructor
+    //============================================================================
+    function new (
+      virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if,
+      virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if,
+      virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if,
+
+      virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if,
+
+      virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if,
+      virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if,
+
+      virtual interface clk_if input_clk_if,
+      virtual interface clk_if output_clk_if,
+
+      virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, input_axis)) input_axis_vip_if,
+      virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, output_axis)) output_axis_vip_if
+    );
+
+      // creating the agents
+      super.new(sys_clk_vip_if, 
+                dma_clk_vip_if, 
+                ddr_clk_vip_if, 
+                sys_rst_vip_if, 
+                mng_vip_if, 
+                ddr_vip_if);
+
+      this.input_clk_if = input_clk_if;
+      this.output_clk_if = output_clk_if;
+
+      input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if);
+      output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if);
+
+      input_axis_seq = new(input_axis_agent);
+      output_axis_seq = new(output_axis_agent);
+
+      input_axis_mon = new("Input AXIS Transaction Monitor", input_axis_agent);
+      output_axis_mon = new("Output AXIS Transaction Monitor", output_axis_agent);
+
+      scoreboard_inst = new("Verification Environment Scoreboard");
+
+    endfunction
+
+    //============================================================================
+    // Configure environment
+    //============================================================================
+    task configure();
+
+      // configuration for input
+      this.input_axis_seq.set_stop_policy(STOP_POLICY_PACKET);
+      this.input_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR);
+      this.input_axis_seq.set_descriptor_gen_mode(1);
+      this.input_axis_seq.set_data_beat_delay(0);
+      this.input_axis_seq.set_descriptor_delay(0);
+      this.input_axis_seq.set_inactive_drive_output_0();
+
+      // configuration for output
+      this.output_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE);
+
+      // this.output_axis_seq.set_use_variable_ranges();
+      // this.output_axis_seq.set_high_time_range(1,1);
+      // this.output_axis_seq.set_low_time_range(0,0);
+
+      // this.output_axis_seq.clr_use_variable_ranges();
+      // this.output_axis_seq.set_high_time(1);
+      // this.output_axis_seq.set_low_time(1);
+
+    endtask
+
+    //============================================================================
+    // Start environment
+    //   - Connect all the agents to the scoreboard
+    //   - Start the agents
+    //============================================================================
+    task start();
+
+      super.start();
+
+      input_clk_if.start_clock($urandom_range(1000,10000));
+      output_clk_if.start_clock($urandom_range(1000,10000));
+
+      input_axis_agent.start_master();
+      output_axis_agent.start_slave();
+
+      scoreboard_inst.set_source_stream(input_axis_mon);
+      scoreboard_inst.set_sink_stream(output_axis_mon);
+
+    endtask
+
+    //============================================================================
+    // Start the test
+    //   - start the RX scoreboard and sequencer
+    //   - start the TX scoreboard and sequencer
+    //   - setup the RX DMA
+    //   - setup the TX DMA
+    //============================================================================
+    task test();
+
+      fork
+        input_axis_seq.run();
+        output_axis_seq.run();
+
+        input_axis_mon.run();
+        output_axis_mon.run();
+
+        scoreboard_inst.run();
+      join_none
+
+    endtask
+
+
+    //============================================================================
+    // Post test subroutine
+    //============================================================================
+    task post_test();
+      // Evaluate the scoreboard's results
+    endtask
+
+    //============================================================================
+    // Run subroutine
+    //============================================================================
+    task run;
+
+      //pre_test();
+      test();
+
+    endtask
+
+    //============================================================================
+    // Stop subroutine
+    //============================================================================
+    task stop;
+
+      super.stop();
+
+      input_axis_seq.stop();
+      input_axis_agent.stop_master();
+      output_axis_agent.stop_slave();
+
+      post_test();
+
+    endtask
+
+  endclass
+
+endpackage

util_axis_fifo_asym/system_bd.tcl

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+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+global ad_hdl_dir
+
+source ../../scripts/adi_env.tcl
+
+# system level parameters
+global ad_project_params
+
+set INPUT_WIDTH $ad_project_params(INPUT_WIDTH)
+set OUTPUT_WIDTH $ad_project_params(OUTPUT_WIDTH)
+
+# input clock and reset
+create_bd_port -dir I input_clk
+
+# output clock and reset
+create_bd_port -dir I output_clk
+
+
+ad_ip_instance util_axis_fifo_asym util_axis_fifo_asym_DUT [list \
+  ASYNC_CLK 1 \
+  S_DATA_WIDTH $INPUT_WIDTH \
+  S_ADDRESS_WIDTH 5 \
+  M_DATA_WIDTH $OUTPUT_WIDTH \
+  M_AXIS_REGISTERED 1 \
+  ALMOST_EMPTY_THRESHOLD 4 \
+  ALMOST_FULL_THRESHOLD 4 \
+  TLAST_EN 1 \
+  TKEEP_EN 1 \
+  S_FIFO_LIMITED 0 \
+]
+
+ad_connect input_clk util_axis_fifo_asym_DUT/s_axis_aclk
+ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/s_axis_aresetn
+
+ad_connect output_clk util_axis_fifo_asym_DUT/m_axis_aclk
+ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/m_axis_aresetn
+
+ad_ip_instance axi4stream_vip input_axis [list \
+  INTERFACE_MODE {MASTER} \
+  HAS_TREADY {1} \
+  HAS_TLAST {1} \
+  HAS_TKEEP {1} \
+  TDATA_NUM_BYTES [expr {$INPUT_WIDTH/8}] \
+]
+adi_sim_add_define "INPUT_AXIS=input_axis"
+
+ad_connect input_clk input_axis/aclk
+ad_connect sys_cpu_resetn input_axis/aresetn
+
+ad_connect util_axis_fifo_asym_DUT/s_axis input_axis/m_axis
+
+ad_ip_instance axi4stream_vip output_axis [list \
+  INTERFACE_MODE {SLAVE} \
+  TDATA_NUM_BYTES [expr {$OUTPUT_WIDTH/8}] \
+  HAS_TLAST {1} \
+]
+adi_sim_add_define "OUTPUT_AXIS=output_axis"
+
+ad_connect output_clk output_axis/aclk
+ad_connect sys_cpu_resetn output_axis/aresetn
+
+ad_connect util_axis_fifo_asym_DUT/m_axis output_axis/s_axis