pwm_gen: Initial commit

Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
analogdevicesinc · Nov 12, 2023 · 4357752 · 4357752
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diff --git a/pwm_gen/Makefile b/pwm_gen/Makefile
@@ -0,0 +1,57 @@
+####################################################################################
+####################################################################################
+## Copyright 2023(c) Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# All test-bench dependencies except test programs
+SV_DEPS += ../common/sv/utils.svh
+SV_DEPS += ../common/sv/logger_pkg.sv
+SV_DEPS += ../common/sv/reg_accessor.sv
+SV_DEPS += ../common/sv/m_axis_sequencer.sv
+SV_DEPS += ../common/sv/s_axis_sequencer.sv
+SV_DEPS += ../common/sv/m_axi_sequencer.sv
+SV_DEPS += ../common/sv/s_axi_sequencer.sv
+SV_DEPS += ../common/sv/adi_regmap_pkg.sv
+SV_DEPS += ../common/sv/adi_regmap_common_pkg.sv
+SV_DEPS += ../common/sv/adi_regmap_pwm_gen_pkg.sv
+SV_DEPS += ../common/sv/test_harness_env.sv
+SV_DEPS += system_tb.sv
+
+ENV_DEPS +=../../library/util_cdc/sync_bits.v
+ENV_DEPS +=../../library/common/ad_edge_detect.v
+ENV_DEPS += system_project.tcl
+ENV_DEPS += system_bd.tcl
+ENV_DEPS +=../scripts/adi_sim.tcl
+ENV_DEPS +=../scripts/run_sim.tcl
+
+LIB_DEPS += axi_pwm_gen
+
+# default test program
+TP := test_program
+
+# config files should have the following format
+#  cfg_<param1>_<param2>.tcl
+CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
+#$(warning $(CFG_FILES))
+
+# List of tests and configuration combinations that has to be run
+# Format is:  <configuration>:<test name>
+TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
+#TESTS += cfg1_mm2mm_default:directed_test
+#TESTS += cfg1:test_program
+#TESTS += cfg2_fsync:test_program
+#TESTS += cfg2_fsync:test_frame_delay
+
+include ../scripts/project-sim.mk
+
+# usage :
+#
+# run specific test on a specific configuration in gui mode
+# 	make CFG=cfg2_fsync TST=test_frame_delay MODE=gui
+#
+# run all test from a configuration
+# 	make cfg1_mm2mm_default
+
+####################################################################################
+####################################################################################
diff --git a/pwm_gen/README.md b/pwm_gen/README.md
@@ -0,0 +1,27 @@
+Usage :
+
+Run all tests in batch mode:
+
+	make
+
+
+Run all tests in GUI mode:
+
+	make MODE=gui
+
+
+Run specific test on a specific configuration in gui mode:
+
+	make CFG=<name of cfg> TST=<name of test> MODE=gui
+
+
+Run all test from a configuration:
+
+	make <name of cfg>
+
+
+Where:
+
+ * <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
+ * <name of test> is a file from the tests directory without the tcl extension
+
diff --git a/pwm_gen/cfgs/cfg1.tcl b/pwm_gen/cfgs/cfg1.tcl
@@ -0,0 +1,3 @@
+global ad_project_params
+
+
diff --git a/pwm_gen/system_bd.tcl b/pwm_gen/system_bd.tcl
@@ -0,0 +1,97 @@
+# ***************************************************************************
+# ***************************************************************************
+# Copyright 2023 (c) Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+source ../../scripts/adi_env.tcl
+
+# common zed-based bd for test
+#source ../../projects/common/zed/zed_system_bd.tcl
+
+#  ------------------
+#
+# Block under test 
+#
+#  ------------------
+
+create_bd_port -dir O pwm_gen_o_0
+create_bd_port -dir O pwm_gen_o_1
+create_bd_port -dir O pwm_gen_o_2
+create_bd_port -dir O pwm_gen_o_3
+create_bd_port -dir O pwm_gen_o_4
+create_bd_port -dir O pwm_gen_o_5
+create_bd_port -dir O pwm_gen_o_6
+create_bd_port -dir O pwm_gen_o_7
+create_bd_port -dir O pwm_gen_o_8
+create_bd_port -dir O pwm_gen_o_9
+create_bd_port -dir O pwm_gen_o_10
+create_bd_port -dir O pwm_gen_o_11
+create_bd_port -dir O pwm_gen_o_12
+create_bd_port -dir O pwm_gen_o_13
+create_bd_port -dir O pwm_gen_o_14
+create_bd_port -dir O pwm_gen_o_15
+
+ad_ip_instance axi_pwm_gen dut_pwm_gen
+ad_ip_parameter dut_pwm_gen CONFIG.ASYNC_CLK_EN 1
+ad_ip_parameter dut_pwm_gen CONFIG.N_PWMS 16
+
+
+ad_connect ddr_clk_vip/clk_out dut_pwm_gen/ext_clk
+adi_project_files [list \
+	"../../library/common/ad_edge_detect.v" \
+	"../../library/util_cdc/sync_bits.v"]
+
+ad_connect pwm_gen_o_0 dut_pwm_gen/pwm_0
+ad_connect pwm_gen_o_1 dut_pwm_gen/pwm_1
+ad_connect pwm_gen_o_2 dut_pwm_gen/pwm_2
+ad_connect pwm_gen_o_3 dut_pwm_gen/pwm_3
+ad_connect pwm_gen_o_4 dut_pwm_gen/pwm_4
+ad_connect pwm_gen_o_5 dut_pwm_gen/pwm_5
+ad_connect pwm_gen_o_6 dut_pwm_gen/pwm_6
+ad_connect pwm_gen_o_7 dut_pwm_gen/pwm_7
+ad_connect pwm_gen_o_8 dut_pwm_gen/pwm_8
+ad_connect pwm_gen_o_9 dut_pwm_gen/pwm_9
+ad_connect pwm_gen_o_10 dut_pwm_gen/pwm_10
+ad_connect pwm_gen_o_11 dut_pwm_gen/pwm_11
+ad_connect pwm_gen_o_12 dut_pwm_gen/pwm_12
+ad_connect pwm_gen_o_13 dut_pwm_gen/pwm_13
+ad_connect pwm_gen_o_14 dut_pwm_gen/pwm_14
+ad_connect pwm_gen_o_15 dut_pwm_gen/pwm_15
+
+# connect resets
+
+ad_cpu_interconnect 0x7c000000 dut_pwm_gen
+
+create_bd_port -dir O sys_clk
+
+ad_connect sys_clk sys_cpu_clk
diff --git a/pwm_gen/system_project.tcl b/pwm_gen/system_project.tcl
@@ -0,0 +1,42 @@
+source ../scripts/adi_sim.tcl
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+if {$argc < 1} {
+  puts "Expecting at least one argument that specifies the test configuration"
+  exit 1
+} else {
+  set cfg_file [lindex $argv 0]
+}
+
+# Read config file 
+source "cfgs/${cfg_file}"
+
+# Set the project name
+set project_name [file rootname $cfg_file]
+
+# Create the project
+adi_sim_project_xilinx $project_name "xc7z020clg484-1"
+
+# Add test files to the project
+adi_sim_project_files [list \
+ "../common/sv/utils.svh" \
+ "../common/sv/logger_pkg.sv" \
+ "../common/sv/reg_accessor.sv" \
+ "../common/sv/m_axis_sequencer.sv" \
+ "../common/sv/s_axis_sequencer.sv" \
+ "../common/sv/m_axi_sequencer.sv" \
+ "../common/sv/s_axi_sequencer.sv" \
+ "../common/sv/adi_regmap_pkg.sv" \
+ "../common/sv/adi_regmap_common_pkg.sv" \
+ "../common/sv/adi_regmap_pwm_gen_pkg.sv" \
+ "../common/sv/adi_peripheral_pkg.sv" \
+ "../common/sv/test_harness_env.sv" \
+ "tests/test_program.sv" \
+ "system_tb.sv" \
+ ]
+
+#set a default test program
+adi_sim_add_define "TEST_PROGRAM=test_program"
+
+adi_sim_generate $project_name
diff --git a/pwm_gen/system_tb.sv b/pwm_gen/system_tb.sv
@@ -0,0 +1,99 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014-2023 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsabilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+`include "utils.svh"
+
+module system_tb();
+  wire pwm_gen_o_0;
+  wire pwm_gen_o_1;
+  wire pwm_gen_o_2;
+  wire pwm_gen_o_3;
+  wire pwm_gen_o_4;
+  wire pwm_gen_o_5;
+  wire pwm_gen_o_6;
+  wire pwm_gen_o_7;
+  wire pwm_gen_o_8;
+  wire pwm_gen_o_9;
+  wire pwm_gen_o_10;
+  wire pwm_gen_o_11;
+  wire pwm_gen_o_12;
+  wire pwm_gen_o_13;
+  wire pwm_gen_o_14;
+  wire pwm_gen_o_15;
+
+  wire sys_clk;
+
+  `TEST_PROGRAM test(
+    .pwm_gen_o_0 (pwm_gen_o_0),
+    .pwm_gen_o_1 (pwn_gen_o_1),
+    .pwm_gen_o_2 (pwm_gen_o_2),
+    .pwm_gen_o_3 (pwm_gen_o_3),
+    .pwm_gen_o_4 (pwm_gen_o_4),
+    .pwm_gen_o_5 (pwm_gen_o_5),
+    .pwm_gen_o_6 (pwm_gen_o_6),
+    .pwm_gen_o_7 (pwm_gen_o_7),
+    .pwm_gen_o_8 (pwm_gen_o_8),
+    .pwm_gen_o_9 (pwn_gen_o_9),
+    .pwm_gen_o_10 (pwm_gen_o_10),
+    .pwm_gen_o_11 (pwm_gen_o_11),
+    .pwm_gen_o_12 (pwm_gen_o_12),
+    .pwm_gen_o_13 (pwm_gen_o_13),
+    .pwm_gen_o_14 (pwm_gen_o_14),
+    .pwm_gen_o_15 (pwm_gen_o_15),
+
+    .sys_clk (sys_clk));
+
+  test_harness `TH (
+    .pwm_gen_o_0 (pwm_gen_o_0),
+    .pwm_gen_o_1 (pwn_gen_o_1),
+    .pwm_gen_o_2 (pwm_gen_o_2),
+    .pwm_gen_o_3 (pwm_gen_o_3),
+    .pwm_gen_o_4 (pwm_gen_o_4),
+    .pwm_gen_o_5 (pwm_gen_o_5),
+    .pwm_gen_o_6 (pwm_gen_o_6),
+    .pwm_gen_o_7 (pwm_gen_o_7),
+    .pwm_gen_o_8 (pwm_gen_o_8),
+    .pwm_gen_o_9 (pwn_gen_o_9),
+    .pwm_gen_o_10 (pwm_gen_o_10),
+    .pwm_gen_o_11 (pwm_gen_o_11),
+    .pwm_gen_o_12 (pwm_gen_o_12),
+    .pwm_gen_o_13 (pwm_gen_o_13),
+    .pwm_gen_o_14 (pwm_gen_o_14),
+    .pwm_gen_o_15 (pwm_gen_o_15),
+    .sys_clk (sys_clk));
+
+endmodule