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Add ADF4382 #2096
Add ADF4382 #2096
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some general comments:
- please sign the CLA
- for the documentation build - please add the documentation into the ToC (an example here: 5100411 )
- for the xilinx build make sure that the hardware naming in the build.json file is corresponding to the hdl output name and the project is available on main hdl branch.
- a project README.rst would be nice (see example here: 6673e20 )
I'll remove the Xilinx platform as it is not officially supported yet. |
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some comments on my side.
drivers/frequency/adf4382/adf4382.c
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* @brief Implementation of adf4382 Driver. | ||
* @author Ciprian Hegbeli (ciprian.hegbeli@analog.com) | ||
******************************************************************************** | ||
* Copyright 2023(c) Analog Devices, Inc. |
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2024 :)
drivers/frequency/adf4382/adf4382.c
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#include "no_os_print_log.h" | ||
#include "no_os_delay.h" | ||
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//Charge pump current values expressed in uA |
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nit: c-style comments are preferred even for single line.
drivers/frequency/adf4382/adf4382.c
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ret = no_os_spi_write_and_read(dev->spi_desc, buff, | ||
ADF4382_BUFF_SIZE_BYTES); | ||
if(ret < 0) |
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if (ret)
same as it is done for linux drivers.
drivers/frequency/adf4382/adf4382.c
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*data = buff[2]; | ||
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return ret; |
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return 0;
same as it is done for linux drivers.
tmp = orig & ~mask; | ||
tmp |= data & mask; | ||
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if (tmp != orig) |
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this check is a bit uncommon. but i'm fine with it also.
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adapted the function from the Linux implementation https://elixir.bootlin.com/linux/latest/source/drivers/base/regmap/regmap.c#L3137
return -EINVAL; | ||
adf4382_get_ref_clk(adf4382, &val); | ||
return snprintf(buf, len, "%"PRIu64, val); | ||
// return 0; |
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drop this.
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val = en; | ||
return iio_format_value(buf, len, IIO_VAL_INT, 1, &val); | ||
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drop extra line.
# Select the example you want to enable by chossing y for enabling and n for disabling | ||
BASIC_EXAMPLE = n | ||
IIO_EXAMPLE = y | ||
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nit: drop extra line
.spi_clk_pin = SDP_SPI_SCK, | ||
.use_sw_csb = false | ||
}; | ||
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drop extra lines.
$(PLATFORM_DRIVERS)/stm32_irq.c \ | ||
$(PLATFORM_DRIVERS)/stm32_gpio_irq.c \ | ||
$(PLATFORM_DRIVERS)/stm32_uart.c \ | ||
$(PLATFORM_DRIVERS)/stm32_uart_stdio.c |
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add new line.
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some remarks from my side, also please fix the documentation issues. you will have to provide extra files for the build to be successful, see this example: fd31fb2#diff-d7a16ebb8ac2559dcec7cfb925b059c3176c69cbe2debf591de4d671a11e65dd
also, project documentation can be useful, you may see this example: https://github.com/analogdevicesinc/no-OS/blob/main/projects/eval-adis1650x/README.rst
projects/adf4382/builds.json
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}, | ||
"stm32": { | ||
"basic_example": { | ||
"flags" : "BASIC_EXAMPLE=y" |
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please add also the hardware flag: HARDWARE=sdp-ck1z.ioc
projects/adf4382/builds.json
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"flags" : "BASIC_EXAMPLE=y" | ||
}, | ||
"iio": { | ||
"flags": "IIO_EXAMPLE=y" |
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please add also the hardware flag: HARDWARE=sdp-ck1z.ioc
projects/adf4382/sdp-ck1z.ioc
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MxCube.Version=6.8.1 | ||
MxDb.Version=DB.6.0.81 |
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MxCube.Version=6.5.0
MxDb.Version=DB.6.0.50
return ret; | ||
error: | ||
pr_info("Error!\n"); | ||
return ret; |
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adf4382_remove should be called before returning to free the allocated memory
if (ret) | ||
return ret; | ||
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return iio_app_run(app); |
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there are some memory leaks here, the according remove functions should be called if memory is allocated successfully. you may take a look at: https://github.com/analogdevicesinc/no-OS/blob/main/projects/max14916/src/examples/iio_example/iio_example.c and follow the example
drivers/frequency/adf4382/adf4382.c
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if (pol < 0) | ||
return pol; |
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this will never be true, pol is uint8_t, always >= 0, please adapt accordingly
drivers/frequency/adf4382/adf4382.c
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* @return - 0 in case bits are not set, positive value if they are set | ||
* or negative error code otherwise. | ||
*/ | ||
int adf4382_spi_test_bits(struct adf4382_dev *dev, uint16_t reg_addr, |
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the return type should be the execution status of the API. pass the result by pointer in the parameters list
uint32_t *readval) | ||
{ | ||
return adf4382_spi_read(dev->adf4382_dev, (uint16_t)reg, | ||
(uint8_t *)readval); |
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casting this pointer will result in a different value based on the endianness of the CPU. please do not make the cast
intptr_t priv) | ||
{ | ||
struct adf4382_iio_dev *iio_adf4382 = (struct adf4382_iio_dev *)dev; | ||
struct adf4382_dev *adf4382 = iio_adf4382->adf4382_dev; |
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this should be done after the null check of iio_adf4382, please see all occurrences in the file
V1 -> V2
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there are some conflicts that need addressing.
b11f7b5
to
053c4fb
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drivers/frequency/adf4382/adf4382.c
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return EINVAL; | ||
} | ||
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/*Phase adjustment can only be done if bleed is active, and a bleed |
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there is some inconsistency here in how you wrote comments with // or with /*, please make them look alike
drivers/frequency/adf4382/adf4382.c
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device->clkout_div_reg_val_max = ADF4382A_CLKOUT_DIV_REG_VAL_MAX; | ||
break; | ||
default: | ||
return -EINVAL; |
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you've already allocated something, you'll need to goto
to a label to avoid memory leaks
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Looks good, some minor remarks above.
One more thing, Ramona commented about the gcd() function, (like her) I think you should use the util.h one and remove your implementation unless there is a justification for keeping it which would go in a code comment.
Unfortunately the function in no_os_util.h has a slow execution time which is visible in this driver due to the large numbers which are being processed. I could make a new PR for the gcd replacing the one we currently have, if that is something that would help us. |
drivers/frequency/adf4382/adf4382.c
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ret = no_os_spi_remove(dev->spi_desc); | ||
if (ret) | ||
return ret; |
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no_os_free(dev);
if (index < 0) | ||
return index; |
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index is unsigned, this will never be true
$(PLATFORM_DRIVERS)/stm32_gpio_irq.c \ | ||
$(PLATFORM_DRIVERS)/stm32_uart.c \ | ||
$(PLATFORM_DRIVERS)/stm32_uart_stdio.c | ||
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missing new line at the end of file
@chegbeli It doesn't seem like the driver checks for the PLL actually locking. REG 0x58 (bit 0). After initialization it should be the final check. |
drivers/frequency/adf4382/adf4382.c
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int adf4382_reg_dump(struct adf4382_dev *dev) | ||
{ | ||
uint8_t val; | ||
uint8_t ret; |
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if ret can take negative values, then use int
type. Check throughout the code, since this is occuring multiple times.
drivers/frequency/adf4382/adf4382.c
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ret = no_os_spi_write_and_read(dev->spi_desc, buff, | ||
ADF4382_BUFF_SIZE_BYTES); | ||
if(ret) |
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please follow the linux guidelines -> if (ret)
Check the entire code since there are multiple occurences. Same applies for other statements (for
, while
, switch
etc).
V2 -> V3
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The ADF4382A is a high performance, ultralow jitter, Frac-N PLL with integrated VCO ideally suited for LO generation for 5G applications or data converter clock applications. The high performance PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and high PFD frequency of 625MHz in integer mode that can achieve ultralow in-band noise and integrated jitter. The ADF4382A can generate frequencies in a fundamental octave range of 11.5 GHz to 21 GHz, thereby eliminating the need for sub-harmonic filters. The divide by 2 and 4 output dividers on the part allow frequencies to be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz respectively. Signed-off-by: chegbeli <ciprian.hegbeli@analog.com>
The IIO driver will enable support for the ADF4382 to be used with the IIO framework over the serial interface. This will expose runtime configurable attributes of the IC using the IIO tools. Signed-off-by: chegbeli <ciprian.hegbeli@analog.com>
Add documentation for adf4382 drivers. Signed-off-by: chegbeli <ciprian.hegbeli@analog.com>
Add example projects for the adf4382 using stm32, and mbed platforms. This also includes the example project for IIO as well. The projects have been tested using the EV-ADF4382SD1Z and SDP-K1 for the stm32 and mbed platforms. Signed-off-by: chegbeli <ciprian.hegbeli@analog.com>
Add README.rst documentation file for project alongside other documentation related files. Signed-off-by: chegbeli <ciprian.hegbeli@analog.com>
* @return i - The index of the pair if found or an error if there is no | ||
* pair of values in the table. | ||
*/ | ||
static int adf4382_iio_find_2d_row(const int (*tbl)[2], const int size, |
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You may use ci_table
directly in this function without needing to pass it as a parameter.
Pull Request Description
The ADF4382A is a high performance, ultralow jitter, Frac-N PLL
with integrated VCO ideally suited for LO generation for 5G applications
or data converter clock applications. The high performance
PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and
high PFD frequency of 625MHz in integer mode that can achieve
ultralow in-band noise and integrated jitter. The ADF4382A can
generate frequencies in a fundamental octave range of 11.5 GHz to
21 GHz, thereby eliminating the need for sub-harmonic filters. The
divide by 2 and 4 output dividers on the part allow frequencies to
be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz
respectively.
PR Type
PR Checklist