RISC-V assembler for the University of Warwick FPGA RISC-V core

Hello!

This is dcsembler, a basic assembler for the DCS’s (Department of Computer Science) FPGA soft-core RISC-V project in 2022.

This forms part of the software tooling for the project.

The project is built using CMake, so you’ll need that.

Then, there are handy scripts to help you configure and build and run/test the project.

You can use configure.sh to run CMake automatically, or configure-gui.sh to get a terminal interface for the same.

Then, you’re free to build.sh and run.sh away!

MIT licensed - feel free to use for fun or profit!

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
build		build
cmake		cmake
include/structopt		include/structopt
sandbox		sandbox
src		src
test		test
.gitignore		.gitignore
CMakeLists.txt		CMakeLists.txt
LICENSE		LICENSE
README.org		README.org
assemble-riscv-using-gcc.sh		assemble-riscv-using-gcc.sh
build-doxygen.sh		build-doxygen.sh
build.sh		build.sh
buildrun.sh		buildrun.sh
clean.sh		clean.sh
compile_commands.json		compile_commands.json
configure-gui.sh		configure-gui.sh
configure.sh		configure.sh
notes.org		notes.org
onetwo.S		onetwo.S
open-documentation.sh		open-documentation.sh
run.sh		run.sh
test.sh		test.sh