GitHub - aditi1191998/ICCAD-20---Combinational-Equivalence-Checking

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Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
Makefile		Makefile
README		README
a.v		a.v
b.v		b.v
cada0080		cada0080
cec.c		cec.c
functions.c		functions.c
functions.h		functions.h
keywords.h		keywords.h
to_cnf.py		to_cnf.py
verilog-parser.c		verilog-parser.c

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 A combinational equivalence checker which considers "Dont Care(X)" conditions as well.

  How to run the program?
  ------------------
  Put the verilog files to be compared in the directory.
  cd Final_CEC_Ex
  bash ./cada0080 <filename_1> <filename_2> input_name
  
  
  For further information, contact:
  --------
  Aditi Rakesh Singh
  aditirsingh9@gmail.com