This repository presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from system clock. If we increase the baud rate, speed of serial data transmission increases. As the dividing factor decrease baud rate increases. in this paper we set the system clock frequency as 50MHz and time to transfer each data bit is 23.75ns with baud rate of 42.1 Mbps (dividing factor is 32). Due to increase in the baud rate the time taken to transfer the data decreases, so it is very useful for faster communication devices. Transmitter and Receiver blocks designed by algorithm state machine method simulated in ModelSim, synthesized in Design Compiler, and extracted in ICC in Nangate 45 nm CMOS cell library.
It is a 40-pin-pad-frame communication chip that integrated a transmitter and a receiver, implementing the UART protocol in 6-stage FSM based on 2-phase clocking.
In this project, I went through the whole ASIC design flow:
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Front-end coding in Verilog (./rtl)
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Pre-simulation in Modelsim (./Modelsim)
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Synthesis in Design Compiler with TCL (./Syn)
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Post-Synthesis_Simulation (./Post-Synthesis_Simulation)
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Layout in ICC (./Pnr)
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Translate layout in Magic (./Magic)
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Layout verificate in Irsim (./Irsim)
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Cleaned up DRC and LVS Violations using Calibre(./pvr).
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