This repository is designed to hold a variety of demonstration sinewave generators. These sinewave generators have been discussed and used as examples as part of the ZipCPU Blog on zipcpu.com. If you watch carefully, you may find examples here before they are posted, as I'm going to be doing my development here.
The basic approach in this project is that of a software core generator, found in the sw directory. This generator can be used to make logic in the rtl directory.
The reference that I have used to build the CORDIC algorithms within this repository comes from a Cordic Survey, by Ray Andraka.
There have been several blog posts based upon the code within this repository. These include:
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No PI for you!, a discussion of the ideal units of phase within an FPGA.
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How to build the simplest sine-wave in Verilog, based upon a table-based generator
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How to do the same thing, but with only a Quarter-Wave sine table.
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How to use a CORDIC to generate both sines and cosines. Ultimately this is about how to convert from polar to rectangular coordinates as well.
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How to use a CORDIC to calculate an arctan. This is also known as the rectangular to polar conversion mode of the CORDIC.
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A CORDIC testbench for the sine/cosine generation capability
- This test bench depends upon the discussion of statistical quantization effects that will hinder the performance of the CORDIC.
Another post on the ZipCPU blog discussed how a CORDIC can be used to evaluate an improved(?) PWM signal.
If time permits, I have another sine wave generator that uses fewer logic resources than the CORDIC above, but that requires two multiplies and three RAM's--yet doesn't suffer from the phase truncation effects of the CORDIC. I look forward to having the opportunity to post this in the future.
All of the software (Makefile, C++) code in this repository is released under the GPLv3. The Verilog RTL code generated by this core generator is licensed under LGPLv3. If these conditions are not sufficient for your needs, other licenses terms may be purchased.