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QuickRS232

GitHub code size in bytes GitHub issues GitHub Release Date GitHub release (latest by date)

QuickRS232 is a versatile RS232 FPGA Verilog module with following features:

  • Internal data buffering with FIFO builtin in RS232 with parametric FIFO depth;
  • Full-duplex mode (as RS232 standard supports) with parallel Receive (Rx) and Transmit (Tx);
  • Supports either No Flow Control mode or Hardware Flow Control mode (RTS + CTS);

RS232 timing diagrams (115200 bod/s, even parity, no flow control):

RS232 Timing diagrams

FIFO timing diagrams

FIFO Timing diagrams