Update support for openpiton #1
Open
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
* Add support for "high" counter CSRs in 32-bit mode In 32bit mode MCYCLEH, MINSTRETH, CYCLEH, TIMEH and INSTRETH are used to return the most significant 32-bit value of the counters which are now always 64-bit wide. Signed-off-by: Steffen Persvold <spersvold@gmail.com> * Enable writing of MCYCLEH and MINSTRETH CSRs Signed-off-by: Steffen Persvold <spersvold@gmail.com>
* cva6_synth.tcl: fix set_input_delay and set_output_delay tc_sram paths * ariane_tb.cpp;.sv: [Fix tc_srams] change path for user memory preload Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com> Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Signed-off-by: Guillaume Chauvon<guillaume.chauvon@thalesgroup.com>
Several format cleanings: - split load_store_unit.sv to create lsu_bypass.sv - add several "begin" and "end"
…g 3 operands (openhwgroup#925) * re_name.sv: add condition related to CVXIF to rename 3rd operand * cv32a60x_pkg.sv: set CVXIFEn to 1
* Create bug.yaml * Update bug.yaml - Case consistency * Spelling mistakes
Fixes openhwgroup#906 According to the spec: > If accessing pte violates a PMA or PMP check, raise an access-fault > exception corresponding to the original access type. Found by @Phantom1003 and @ProjectDimlight Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>
* Removing CVA6-SDK from task.yaml * Associated PRs in task.yaml This commit provide a new textarea to fill links to PRs used to complete the task. * Create bug.yaml * Update bug.yaml - Case consistency Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
unlike other instructions with minor opcode == PRIV, SFENCE.VMA do not check for rs1 != 0. Only check for rd !=0 to raise illegal instruction Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
…enhwgroup#939) It avoids that result from cvxif and illegal instruction use wb bus at the same time
…enhwgroup#940) see The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 20211203 3.1.1 Hardware Performance Monitor All counters should be implemented, but a legal implementation is to make both the counter and its corresponding event selector be read-only 0. Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
No description provided.