rtlode

An open source tool that can automatically generate logic circuits from a user-friendly configuration file for efficiently solving systems of ODEs on FPGAs.

Supported FPGAs

Currently, only the Intel Programmable Acceleration Card with Intel Arria 10 GX 1150 FPGA using the Intel Acceleration Stack 1.2.1 is supported. If you don't have the required hardware, you can still simulate the logic generated by rtlode (see Simulation).

Installation

If you want only to simulate the generated logic you can skip step 1, 2 and 3.

1. Install OPAE by following the instructions here.

2. Install the OPAE python bindings as described here.

3. Install Quartus Prime and make it availabe in the path.

4. Install additional dependencies required by rtlode:

   pip install -r requirements.txt

5. Optional for co-simulation: Install iverilog and make it available in the path.

Usage

1. Create or adjust configuration files (format.md) for the initial value problem, and the solver method to use. Example configuration files can be found in config.

2. Create a solver unit with given configuration files:

   rtlode.py build heun.yaml predator-prey.yaml

3. To test your solver you can execute the following command:

   rtlode.py run heun_predator-prey.slv --runtime_config='{x: 0, y: [0, 2], n: 60, h: 0.17}'

   Alternativly a simple benchmark can be performed:

   rtlode.py benchmark heun_predator-prey.slv --runtime_config='{x: 0, y: [0, 2], n: 60, h: 0.17}'

Simulation

from generator.generator import simulate
simulate('config/numeric/default_fixed.yaml', 'config/problems/predator-prey.yaml', 'config/methods/heun.yaml')

Co-simulation with iverilog is also possible:

from generator.generator import simulate
simulate('config/numeric/default_fixed.yaml', 'config/problems/predator-prey.yaml', 'config/methods/heun.yaml', cosimulate=True)

To create a verilog file for manual inspection you can call the convert logic directly. The generated files can be found in generator/out/.

from generator.generator import convert, _load_config
convert(_load_config('config/numeric/default_fixed.yaml', 'config/problems/vdpol.yaml', 'config/methods/rk4.yaml'))

Related Articles

• Bartel S, Korch M. Generation of logic designs for efficiently solving ordinary differential equations on field programmable gate arrays. Softw Pract Exper. 2021;1-26. doi: 10.1002/spe.3043

License

rtlode is licensed under the MIT license.