32-bit MIPS Implementation in Verilog

Verilog implementation of a 32-bit MIPS processor inspired by: John Hennessy, David Patterson (2017). Computer Architecture: A Quantitative Approach. Currently supports the following instructions:

• R-Type
  • SLL, SRL, SRA, SLLV, SRLV, SRAV, ADDU, SUBU, AND, OR, XOR, NOR, SLT
• I-Type
  • LB, LH, LW, LWU, LBU, LHU, SB, SH, SW, ADDI, ANDI, ORI, XORI, LUI, SLTI, BEQ, BNE, J, JAL
• J-Type
  • JR, JALR

License

GNU GPLv3

Authors

• Juan Soriano
• Ivan Vignolles