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[SiWx917] Added fixes for 917 SoC timer issue #198
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For the record, what was changed in the project to produce this generated file? Was it just the clock frequency change (a component config, I presume) or some other additional changes? Just trying to understand where the logic changes in soc_pll_config() came from. |
Restyled by clang-format Co-authored-by: Restyled.io <commits@restyled.io>
Hi @selissia , This file |
Will this file work with CSA master? As you are targeting main, will this prevent us from adding other commits on top and bump the submodule on csa ? |
@jmartinez-silabs , I have validated the changes on RC_2.3.0-1.3 and silabs_slc_1.3 , it is working fine. I couldn't test on CSA as CSA is broken on SoC. These are clock related changes , will definitely work on CSA too. |
Problem / Feature
Timers are inconsistent with non-sleepy applications
Change overview
With non-sleepy applications ,RTOS Software Timer drift while using an RC-32MHz as a Core reference Clock. It has been changed to 40MHZ and timers are working accurately
Testing
Tested manually Tc-su_2_01 step 2, tc_su_2_02 step 2, tc_su_2_05 step 3 and tc_su_2_05 step 4