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Functional verification project for the CORE-V family of RISC-V cores.

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core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

NEWS UPDATES:

2021-07-15: The verificaton environment for the cv32e40s is up and running.
2021-03-23: The verificaton environment for the cv32e40x is up and running.
2020-12-16: The cv32e40p_v1.0.0 of core-v-verif is released. This tag clones the v1.0.0 release of the CV32E40P CORE-V core and will allow you to reproduce the verification environment as it existed at RTL Freeze.
More news is available in the archive.

Getting Started

First, have a look at the OpenHW Group's website to learn a bit more about who we are and what we are doing.
For first time users of CORE-V-VERIF, the Quick Start Guide in the CORE-V-VERIF Verification Strategy is the best place to start.

Directory Structure of this Repo

bin

Various utilities for running tests and performing various verification-related activities in the core-v-verif repository.

core-v-cores

Empty sub-directory into which the RTL from one or more of the CORE-V-CORES repositories is cloned.

cv32e40p, cv32e40x, cv32e40s, cva6

Core-specific verification code.

docs

Sources for the Verification Strategy document, DV plans, coding style guidelines and available coverage reports.

mk

Common simulation Makefiles that support testbenches for all CORE-V cores.

lib

Common components for the all CORE-V verification environments.

vendor_lib

Verification components supported by third-parties.

Contributing

We highly appreciate community contributions. You can get a sense of our current needs by reviewing the GitHub projects associated with this repository. Individual work-items within a project are defined as issues with a task label.

To ease our work of reviewing your contributions, please:

  • Review CONTRIBUTING and our SV/UVM coding style guidelines.
  • Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
  • Write meaningful commit messages.
  • If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.

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Functional verification project for the CORE-V family of RISC-V cores.

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