Releases: RoaLogic/RV12
v1.3: RV12 32/64 Bit RISC-V CPU
Summary
Highly configurable single-issue, single-core RV32I, RV64I compliant RISC-V CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses, featuring an optimizing folded 6-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
Changes
New Features
- Full Support for Privileged Spec v1.10 and User Spec v 2.2
- Higher performance 6 stage pipeline
- Physical Memory Protection Block support
Release Notes
- Documentation fully updated
- PDF Datasheet
Bug Fixes
Below is a summary of key issues addressed. See GitHub Release Milestone for a full list & details.
v1.3: RV12 32/64 Bit RISC-V CPU - RC #2
Summary
Highly configurable single-issue, single-core RV32I, RV64I compliant RISC-V CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses, featuring an optimizing folded 6-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
Changes
New Features
- Full Support for Privileged Spec v1.10 and User Spec v 2.2
- Higher performance 6 stage pipeline
Release Notes
- Documentation fully updated
- Physical Memory Protection Block support
Bug Fixes
Below is a summary of key issues addressed. See GitHub Release Milestone for a full list & details.
v1.3: RV12 32/64 Bit RISC-V CPU - RC #1
Summary
Highly configurable single-issue, single-core RV32I, RV64I compliant RISC-V CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses, featuring an optimizing folded 6-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
Changes
New Features
- Full Support for Privileged Spec v1.10 and User Spec v 2.2
- Higher performance 6 stage pipeline
Release Notes
- Documentation partially updated (missing CSR update info)
- Physical Memory Protection Block not yet included
Bug Fixes
Below is a summary of key issues addressed. See GitHub Release Milestone for a full list & details.
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v1.2: RV12 32/64 Bit RISC-V CPU - Bug Fix #1
Summary
Description
Highly configurable single-issue, single-core RV32I, RV64I compliant RISC-V CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses, featuring an optimizing folded 4-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
New Features
- None
Release Notes / Bug Fixes
- Remove README reference to Wishbone Interface (Not yet added to core)
- Remove spurious swap files from respository
(Datasheet unchanged, remains at v1.1)
v1.1: RV12 32/64 Bit RISC-V CPU - Initial Release
Summary
Description
Highly configurable single-issue, single-core RV32I, RV64I compliant RISC-V CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses, featuring an optimizing folded 4-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
Optional features
- Branch Prediction
- Instruction and Data Caches
- Data Cache
Parameterised and configurable features
- Instruction and data interfaces
- Branch-prediction-unit configuration
- Cache size, associativity, and replacement algorithms.
Release Notes:
- First Full Source Code & Documentation Release for Roa Logic RV12 CPU
- Full Support for Privileged Spec v1.9.1 and User Spec v 2.2
- See Roa Logic Web Site for more information