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drivers/mtd_spi_nor: removed Kconfig & added MX/ISSI security features
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crasbe committed Apr 17, 2024
1 parent 7f550ac commit c293317
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Showing 6 changed files with 378 additions and 56 deletions.
1 change: 0 additions & 1 deletion drivers/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,6 @@ endmenu # Sensor Device Drivers

menu "Storage Device Drivers"
rsource "mtd_sdcard/Kconfig"
rsource "mtd_spi_nor/Kconfig"
endmenu # Storage Device Drivers

endmenu # Drivers
69 changes: 49 additions & 20 deletions drivers/include/mtd_spi_nor.h
Original file line number Diff line number Diff line change
Expand Up @@ -36,24 +36,6 @@ extern "C"
{
#endif

#define STATUS_WIP 0x01u
#define STATUS_WEL 0x02u
#define STATUS_BP0 0x04u
#define STATUS_BP1 0x08u
#define STATUS_BP2 0x10u
#define STATUS_BP3 0x20u
#define STATUS_QE 0x40u
#define STATUS_SRWD 0x80u

#define SECURITY_SOTP 0x01u
#define SECURITY_LDSO 0x02u
#define SECURITY_PSB 0x04u
#define SECURITY_ESB 0x08u
#define SECURITY_XXXXX 0x10u
#define SECURITY_PFAIL 0x20u
#define SECURITY_EFAIL 0x40u
#define SECURITY_WPSEL 0x80u

/**
* @brief SPI NOR flash opcode table
*/
Expand All @@ -71,7 +53,7 @@ typedef struct {
uint8_t chip_erase; /**< Chip erase */
uint8_t sleep; /**< Deep power down */
uint8_t wake; /**< Release from deep power down */
uint8_t rdscur; /**< Read security register */
uint8_t security; /**< Read security register */
} mtd_spi_nor_opcode_t;

/**
Expand Down Expand Up @@ -114,6 +96,17 @@ typedef struct __attribute__((packed)) {
*/
#define SPI_NOR_F_SECT_64K (4)

/**
* @brief Flag to set when the device supports the Macronix security register (rdscur opcode)
*/
#define SPI_NOR_F_MX_SECUR (256)

/**
* @brief Flag to set when the device supports the ISSI security/extended read register
* (rderp opcode)
*/
#define SPI_NOR_F_ISSI_SECUR (512)

/**
* @brief Compile-time parameters for a serial flash device
*/
Expand Down Expand Up @@ -188,7 +181,8 @@ extern const mtd_desc_t mtd_spi_nor_driver;
* The numbers were taken from Micron M25P16, but the same opcodes can
* be found in Macronix MX25L25735E, and multiple other data sheets for
* different devices, as well as in the Linux kernel, so they seem quite
* sensible for default values. */
* sensible for default values.
*/
extern const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default;

/**
Expand All @@ -198,6 +192,41 @@ extern const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default;
*/
extern const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default_4bytes;

/**
* @brief Macronix-specific opcodes including security features
*
* Some Macronix NOR Flashs have a dedicated security register which has flags to indicate
* if the last program/erase operation was successful or not. The RDSCUR opcode is
* used ot access this register, which requires a vendor specific opcode set.
* To utilize this feature, the SPI_NOR_F_MX_SECUR flag has to be set as well.
*/
extern const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_macronix;

/**
* @brief Macronix-specific 4-byte opcodes including security features
*
* Commands for 4-byte address chips (above 128Mb)
*/
extern const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_macronix_4bytes;

/**
* @brief ISSI-specific opcodes including security features
*
* Some ISSI NOR Flashs have a dedicated Extended Read Parameter register which has flags
* to indicate if the last program/erase operation was successful or not.
* The RDERP opcode is used to access this register, which requires a vendor specific
* opcode set.
* To utilize this feature, the SPI_NOR_F_MX_SECUR flag has to be set as well.
*/
extern const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_issi;

/**
* @brief ISSI-specific 4-byte opcodes including security features
*
* Commands for 4-byte address chips (above 128Mb)
*/
extern const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_issi_4bytes;

#ifdef __cplusplus
}
#endif
Expand Down
22 changes: 0 additions & 22 deletions drivers/mtd_spi_nor/Kconfig

This file was deleted.

232 changes: 232 additions & 0 deletions drivers/mtd_spi_nor/include/mtd_spi_nor_defines.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,232 @@
/*
* Copyright (C) 2024 Technische Universität Hamburg
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/

/**
* @ingroup drivers_mtd_spi_nor
* @{
*
* @file
* @brief Definitions for the MTD SPI NOR Flash driver
*
* More detailed information about the file and the functionality implemented.
*
* @author Christopher Büchse <christopher.buechse@tuhh.de>
*
*/

#ifndef MTD_SPI_NOR_DEFINES_H
#define MTD_SPI_NOR_DEFINES_H

#ifdef __cplusplus
extern "C" {
#endif

/**
* @name Common Status Bits from the Status Register of SPI NOR Flashs
* @{
*/
/**
* @brief Write In Progress Flag (R)
*
* 0 - Device is ready
* 1 - Write cycle in progress and device is busy
*/
#define SPI_NOR_STATUS_WIP 0x01u

/**
* @brief Write Enable Latch Flag (R/W)
*
* 0 - Device is not write enabled
* 1 - Device is write enabled
*/
#define SPI_NOR_STATUS_WEL 0x02u

/**
* @brief Block Protection Bit 0 Flag (R/W)
*
* 0 - Specific blocks are not write-protected
* 1 - Specific blocks are write-protected
*/
#define SPI_NOR_STATUS_BP0 0x04u

/**
* @brief Block Protection Bit 1 Flag (R/W)
*
* 0 - Specific blocks are not write-protected
* 1 - Specific blocks are write-protected
*/
#define SPI_NOR_STATUS_BP1 0x08u

/**
* @brief Block Protection Bit 2 Flag (R/W)
*
* 0 - Specific blocks are not write-protected
* 1 - Specific blocks are write-protected
*/
#define SPI_NOR_STATUS_BP2 0x10u

/**
* @brief Block Protection Bit 3 Flag (R/W)
*
* 0 - Specific blocks are not write-protected
* 1 - Specific blocks are write-protected
*/
#define SPI_NOR_STATUS_BP3 0x20u

/**
* @brief Quad Enable Flag (R/W)
*
* 0 - Quad output function disabled
* 1 - Quad output function enabled
*/
#define SPI_NOR_STATUS_QE 0x40u

/**
* @brief Status Register Write Disable Flag (R/W)
*
* 0 - Status Register is not write protected
* 1 - Status Register is write protected
*/
#define SPI_NOR_STATUS_SRWD 0x80u

/** @} */

/**
* @name Macronix Style Security Register Bits
* @note These flags were taken from the MX25L51245G datasheet, but probably apply
* to other devices from Macronix as well.
* @{
*/
/**
* @brief Secured OTP Flag
*
* 0 - OTP area not factory locked
* 1 - OTP area factory locked
*/
#define MX_SECURITY_SOTP 0x01u

/**
* @brief Lock-down Secured OTP Flag
*
* 0 - OTP area not (user) locked
* 1 - OTP area locked (can not be programmed/erased)
*/
#define MX_SECURITY_LDSO 0x02u

/**
* @brief Program Suspend Flag
*
* 0 - Program is not suspended
* 1 - Program suspended
*/
#define MX_SECURITY_PSB 0x04u

/**
* @brief Erase Suspend Flag
*
* 0 - Erase is not suspended
* 1 - Erase is suspended
*/
#define MX_SECURITY_ESB 0x08u

/**
* @brief Reserved
*/
#define MX_SECURITY_XXXXX 0x10u

/**
* @brief Program Fail Flag
*
* 0 - Program Operation succeeded
* 1 - Program Operation failed or region is protected
*/
#define MX_SECURITY_PFAIL 0x20u

/**
* @brief Erase Fail Flag
*
* 0 - Erase Operation succeeded
* 1 - Erase Operation failed or region is protected
*/
#define MX_SECURITY_EFAIL 0x40u

/**
* @brief Write Protection Selection Flag
*
* 0 - Normal Write Protect mode
* 1 - Advanced Sector Protection mode
*/
#define MX_SECURITY_WPSEL 0x80u
/** @} */

/**
* @name ISSI Style Security Register Bits from Extended Read Register (ERP)
* @note These flags were taken from the IS25LE01G datasheet, but probably
* apply to other devices from ISSI as well.
* @{
*/

/**
* @brief Reserved
*/
#define IS_SECURITY_XXXXX 0x01u

/**
* @brief Protection Error Flag (R)
*
* 0 - No protection error
* 1 - Protection Error occurred in program or erase
*/
#define IS_SECURITY_PROT_E 0x02u

/**
* @brief Program Error Flag (R)
*
* 0 - Program Operation succeeded
* 1 - Program Operation failed or region is protected
*/
#define IS_SECURITY_P_ERR 0x04u

/**
* @brief Erase Error Flag (R)
*
* 0 - Erase Operation succeeded
* 1 - Erase Operation failed or region is protected
*/
#define IS_SECURITY_E_ERR 0x08u

/**
* @brief Data Learning Pattern Flag (R/W)
*
* 0 - DLP is disabled
* 1 - DLP is enabled
*/
#define IS_SECURITY_DLPEN 0x10u

/**
* @brief Output Driver Strength Bit 0 (R/W)
*/
#define IS_SECURITY_ODS0 0x20u

/**
* @brief Output Driver Strength Bit 1 (R/W)
*/
#define IS_SECURITY_ODS1 0x40u

/**
* @brief Output Driver Strength Bit 2 (R/W)
*/
#define IS_SECURITY_ODS2 0x80u
/** @} */

#ifdef __cplusplus
}
#endif

#endif /* MTD_SPI_NOR_DEFINES_H */
/** @} */

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