Design Verification and Physical Design of SerDES

This project is oriented towards the RTL design, verification using UVM and Phusical Design of a Quad-lane Full duplex Serializer/Deserializer(SerDes). This work was carried out as the mini project of our M.E VLSI Design, II semester, Manipal School of Information Sciences(MSIS), Manipal.

Team

• Punith P : punithprakash2001@gmail.com : https://www.linkedin.com/in/punith-p/
• Yashasvi : yashasvishetty9697@gmail.com :

Design

All the system verilog design files of various sub components, encoder(8b/10b) , PISO(10b), SIPO, decoder(10b/8b), and the TOP module along with a basic randomized testbenh are provided in the RTL folder. The SerDes.sv is the main SerDes design file, the top.sv file instantiaties this and connects the serializer with deserializer for verification purposes.

UVM Verification

All the UVM objects and components are authored and provided in the UVM folder.Assertions and coverage is implemented in the testbench top. The scoreboard needs further improvement. The following is the snapshot of the simulation of the SerDes module.

Physical Design

45nm fast lib obtained from Cadence website was used for the physical design. The scripts to carry out the Synthesis, Place & route and timing analysis and fixing are provided in the PD folder along with all the results/reports obtained. The synthesized netlist, constraints and delays file generated is also provided.