Skip to content

Commit 6e6b449

Browse files
huxuan0307huxuan0307
committed
Add tval inst tests
1 parent 2231119 commit 6e6b449

File tree

3 files changed

+207
-1
lines changed

3 files changed

+207
-1
lines changed

‎Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ c_srcs := main.c page_tables.c rvh_test.c interrupt_tests.c\
3535
translation_tests.c test_register.c virtual_instruction.c\
3636
hfence_tests.c wfi_tests.c tinst_tests.c\
3737
apt_tests.c\
38+
tval_inst_tests.c\
3839
$(addprefix $(plat_dir)/, $(notdir $(wildcard $(plat_dir)/*.c)))
3940
asm_srcs := boot.S handlers.S $(wildcard $(plat_dir)/*.S)
4041
ld_file:=linker.ld
@@ -61,7 +62,7 @@ $(TARGET).bin: $(TARGET).elf
6162

6263
$(TARGET).elf: $(objs) $(ld_file_final)
6364
$(CC) $(LDFLAGS) -T$(ld_file_final) $(objs) -o $@
64-
$(OBJDUMP) -S $@ > $(TARGET).asm
65+
$(OBJDUMP) -S -d $@ > $(TARGET).asm
6566
$(READELF) -a -W $@ > $(@).txt
6667

6768
$(build_dir)/%.o: %.[c,S] $(build_dir)/%.d

‎test_register.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,3 +12,4 @@ TEST_REGISTER(hfence_test); //need that xiangshan run it alone
1212
TEST_REGISTER(wfi_exception_tests);
1313
TEST_REGISTER(tinst_tests);
1414
TEST_REGISTER(apt_tests);
15+
TEST_REGISTER(tval_inst_tests);

‎tval_inst_tests.c

Lines changed: 204 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,204 @@
1+
#include <rvh_test.h>
2+
3+
bool tval_inst_tests() {
4+
5+
TEST_START();
6+
7+
goto_priv(PRIV_M);
8+
9+
if (false) {
10+
DETAIL("Test mtval when CAUSE_ILI occurs");
11+
12+
CSRW(CSR_MEDELEG, 0);
13+
14+
TEST_SETUP_EXCEPT();
15+
asm volatile(".4byte 0xFFFFFFFF");
16+
TEST_ASSERT(
17+
"check insn 0xFFFFFFFF trap in M mode",
18+
excpt.triggered == true
19+
);
20+
TEST_ASSERT(
21+
"check insn 0xFFFFFFFF trap in M mode: cause is CAUSE_ILI",
22+
excpt.cause == CAUSE_ILI
23+
);
24+
TEST_ASSERT(
25+
"check insn 0xFFFFFFFF trap in M mode: mtval is 0xFFFFFFFF",
26+
excpt.tval == 0xFFFFFFFFUL,
27+
);
28+
goto_priv(PRIV_M);
29+
}
30+
31+
if (false) {
32+
DETAIL("Test stval when CAUSE_ILI occurs");
33+
34+
CSRW(CSR_MEDELEG, 1UL << CAUSE_ILI);
35+
CSRW(CSR_HEDELEG, 0);
36+
goto_priv(PRIV_HS);
37+
38+
TEST_SETUP_EXCEPT();
39+
asm volatile(".4byte 0xFFFFFFFF");
40+
TEST_ASSERT(
41+
"check insn 0xFFFFFFFF trap in HS mode",
42+
excpt.triggered == true
43+
);
44+
TEST_ASSERT(
45+
"check insn 0xFFFFFFFF trap in HS mode: cause is CAUSE_ILI",
46+
excpt.cause == CAUSE_ILI
47+
);
48+
TEST_ASSERT(
49+
"check insn 0xFFFFFFFF trap in HS mode: stval is 0xFFFFFFFF",
50+
excpt.tval == 0xFFFFFFFFUL,
51+
);
52+
goto_priv(PRIV_M);
53+
}
54+
55+
if (false) {
56+
DETAIL("Test vstval when CAUSE_ILI occurs");
57+
58+
CSRW(CSR_MEDELEG, 1UL << CAUSE_ILI);
59+
CSRW(CSR_HEDELEG, 1UL << CAUSE_ILI);
60+
goto_priv(PRIV_VS);
61+
62+
TEST_SETUP_EXCEPT();
63+
asm volatile(".4byte 0xFFFFFFFF");
64+
TEST_ASSERT(
65+
"check insn 0xFFFFFFFF trap in VS mode",
66+
excpt.triggered == true
67+
);
68+
TEST_ASSERT(
69+
"check insn 0xFFFFFFFF trap in VS mode: cause is CAUSE_ILI",
70+
excpt.cause == CAUSE_ILI
71+
);
72+
TEST_ASSERT(
73+
"check insn 0xFFFFFFFF trap in VS mode: vstval is 0xFFFFFFFF",
74+
excpt.tval == 0xFFFFFFFFUL,
75+
);
76+
goto_priv(PRIV_M);
77+
}
78+
79+
if (false) {
80+
DETAIL("Test mtval C ext when CAUSE_ILI occurs");
81+
82+
CSRW(CSR_MEDELEG, 0);
83+
TEST_SETUP_EXCEPT();
84+
85+
asm volatile(".2byte 0x8000");
86+
TEST_ASSERT(
87+
"check insn 0x8000 trap in M mode",
88+
excpt.triggered == true
89+
);
90+
TEST_ASSERT(
91+
"check insn 0x8000 trap in M mode: cause is CAUSE_ILI",
92+
excpt.cause == CAUSE_ILI
93+
);
94+
TEST_ASSERT(
95+
"check insn 0x8000 trap in M mode: mtval is 0x8000",
96+
excpt.tval == 0x8000UL,
97+
);
98+
goto_priv(PRIV_M);
99+
}
100+
101+
if (false) {
102+
DETAIL("Test stval C ext when CAUSE_ILI occurs");
103+
104+
CSRW(CSR_MEDELEG, 1UL << CAUSE_ILI);
105+
CSRW(CSR_HEDELEG, 0);
106+
goto_priv(PRIV_HS);
107+
108+
TEST_SETUP_EXCEPT();
109+
asm volatile(".2byte 0x8000");
110+
TEST_ASSERT(
111+
"check insn 0x8000 trap in HS mode",
112+
excpt.triggered == true
113+
);
114+
TEST_ASSERT(
115+
"check insn 0x8000 trap in HS mode: cause is CAUSE_ILI",
116+
excpt.cause == CAUSE_ILI
117+
);
118+
TEST_ASSERT(
119+
"check insn 0x8000 trap in HS mode: stval is 0x8000",
120+
excpt.tval == 0x8000UL,
121+
);
122+
goto_priv(PRIV_M);
123+
}
124+
125+
if (false) {
126+
DETAIL("Test vstval C ext when CAUSE_ILI occurs");
127+
128+
CSRW(CSR_MEDELEG, 1UL << CAUSE_ILI);
129+
CSRW(CSR_HEDELEG, 1UL << CAUSE_ILI);
130+
goto_priv(PRIV_VS);
131+
132+
TEST_SETUP_EXCEPT();
133+
asm volatile(".2byte 0x8000");
134+
TEST_ASSERT(
135+
"check insn 0x8000 trap in VS mode",
136+
excpt.triggered == true
137+
);
138+
TEST_ASSERT(
139+
"check insn 0x8000 trap in VS mode: cause is CAUSE_ILI",
140+
excpt.cause == CAUSE_ILI
141+
);
142+
TEST_ASSERT(
143+
"check insn 0x8000 trap in VS mode: vstval is 0x8000",
144+
excpt.tval == 0x8000UL,
145+
);
146+
goto_priv(PRIV_M);
147+
}
148+
149+
if (true) {
150+
DETAIL("Test mtval when CAUSE_VRTI occurs");
151+
152+
CSRW(CSR_MEDELEG, 0);
153+
goto_priv(PRIV_VS);
154+
155+
TEST_SETUP_EXCEPT();
156+
hfence_vvma();
157+
158+
TEST_ASSERT(
159+
"check insn hfence.vvma executed in VS mode and traping in M mode",
160+
excpt.triggered == true
161+
);
162+
TEST_ASSERT(
163+
"check insn hfence.vvma executed in VS mode and traping in M mode: cause is CAUSE_VRTI",
164+
excpt.cause == CAUSE_VRTI
165+
);
166+
TEST_ASSERT(
167+
"check insn hfence.vvma executed in VS mode and traping in M mode: mtval is 0x22000073",
168+
excpt.tval == 0x22000073UL,
169+
);
170+
goto_priv(PRIV_M);
171+
}
172+
173+
if (true) {
174+
DETAIL("Test stval when CAUSE_VRTI occurs");
175+
176+
CSRW(CSR_MEDELEG, (1UL << CAUSE_VRTI));
177+
CSRW(CSR_HEDELEG, (1UL << CAUSE_VRTI));
178+
// CAUSE_VRTI cannot be delegated to VS mode
179+
TEST_ASSERT(
180+
"hedeleg.EX_VI should be false",
181+
CSRR(CSR_HEDELEG) == 0
182+
);
183+
goto_priv(PRIV_VS);
184+
185+
TEST_SETUP_EXCEPT();
186+
hfence_vvma();
187+
188+
TEST_ASSERT(
189+
"check insn hfence.vvma executed in VS mode and traping in HS mode",
190+
excpt.triggered == true
191+
);
192+
TEST_ASSERT(
193+
"check insn hfence.vvma executed in VS mode and traping in HS mode: cause is CAUSE_VRTI",
194+
excpt.cause == CAUSE_VRTI
195+
);
196+
TEST_ASSERT(
197+
"check insn hfence.vvma executed in VS mode and traping in HS mode: stval is 0x22000073",
198+
excpt.tval == 0x22000073UL,
199+
);
200+
goto_priv(PRIV_M);
201+
}
202+
203+
TEST_END();
204+
}

0 commit comments

Comments
 (0)