How to generate verilog file for FPGA build?

[kyeoh2]

I am trying to build a FPGA model, any advice how to generate the full system verilog file?

[poemonsense]

We don't provide full-system Verilog file. We provide top-level with 3 AXIs. make verilog generates it.

[kyeoh2]

Thanks, that is good enough.

[kyeoh2]

Thanks for the answer.