Skip to content

opae-sdk-1.0.0
Compare
Choose a tag to compare
@nakulkorde nakulkorde released this 03 May 21:22
· 2989 commits to master since this release
1.0.0-5
66c8bad
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.

The Open Programmable Acceleration Engine is a software framework for managing and accessing programmable accelerators (FPGAs). Its main parts are:

  • The OPAE Software Development Kit (OPAE SDK),

  • the OPAE Linux driver for Intel(R) Xeon(R) CPU with Integrated FPGAs and Intel(R) PAC with Arria(R) 10 GX FPGA

  • the Basic Building Block (BBB) library for accelerating AFU
    development (not part of this release, but pre-release code is
    available on GitHub: [https://github.com/OPAE/intel-fpga-bbb]

OPAE is under active development to extend to more hardware platforms, as well as to build up the software stack with additional abstractions to enable more software developers.

The OPAE SDK is a collection of libraries and tools to facilitate the development of software applications and accelerators using OPAE. It provides a library implementing the OPAE C API for presenting a streamlined and easy-to-use interface for software applications to discover, access, and manage FPGA devices and accelerators using the OPAE software stack. The OPAE SDK also includes the AFU Simulation Environment (ASE) for end-to-end simulation of accelerator RTL together with software applications using the OPAE C API.

OPAE's goal is to accelerate FPGA adoption. It is a community effort to simplify the development and deployment of FPGA applications, so we explicitly welcome discussions and contributions! The OPAE SDK source, unless otherwise noted, is released under a BSD 3-clause license.

More information about OPAE can be found
at http://01.org/OPAE.

Open Programmable Acceleration Engine (OPAE) 1.0.0 Release Notes

This document provides the Release Notes for the Open Programmable
Acceleration Engine (OPAE) 1.0.0 release.

System Compatibility

  • Hardware: tightly coupled FPGA products and programmable FPGA
    acceleration cards for Intel(R) Xeon(R) processors (to be released):

    • Intel(R) PAC with Arria(R) 10 GX FPGA (PCI ID: 0x09c4) FIM version 1.0.3 (1.0 Production)
    • Intel(R) Xeon with Integrated FPGA (PCI ID: 0xbcc0) FIM version 6.4.0

  • Operating System: tested on Red Hat Enterprise Linux 7.3, and CentOS
    7.4, with Linux kernels 3.10 through 4.7

Major Changes from 0.13.1 to 1.0.0

  • Added API functions to retrieve libopae-c version information
  • Added support for vendor ID and device ID properties
  • MMIO mappings are now automatically freed on resource close
  • Reduced minimum supported clock frequency to 25MHz
  • Removed dependency on Boost
  • Added support for building debian packages
  • Building packages sets the default install location to /usr/local
  • Improved error clearing flow in fpgainfo
  • Added RAS support for discrete FPGA devices
  • Improved test coverage
  • Fixed "freq" option for bandwidth calculation in fpgadiag
  • fpgadiag now reads pclock frequency from hardware
  • Improved handling/generation of CCI-P FIFO signals in ASE by providing flexible clock and local memory
  • Improved platform support in the platform database
  • Enabling ASE platform support for tests
  • Improved support for platform database in AFU JSON
  • Updated documentation for build chain, packaging(DEB and RPM) and ASE
  • Reorganized tools directory structure
  • Code cleanup and improved error messages
  • Various bug fixes

Notes / Known Issues

  • A different OPN is used in the design examples

    The Intel Quartus Prime Pro Edition license uses a design example

    OPN of 10AX115N3F40E2SG, instead of the Intel PAC with Intel Arria
    10 GX FPGA OPN of 10AX115N2F40E2LG. This difference does not impact
    your design.

  • PCIe directed speed changes are not supported

    Only automatic down-training at boot time is supported

  • Virtual Function (VF) may fail to attach or detach when using the
    Linux Red Hat 3.10 kernel

    This is a known issue with qemu/kvm and libvirt. Refer to the Red
    Hat website for more information about this issue.

  • The Intel FPGA Dynamic Profiler Tool for OpenCL GUI reports
    frequency and bandwidth incorrectly

    This issue will be resolved in a future version of the Intel
    Acceleration Stack.

  • fpgainfo may raise a UnicodeEncodeError when the Python
    interpreter cannot determine what encoding to use

    This issue typically occurs when redirecting or piping output. The
    fpgabist tool calls fpgainfo and is also impacted.

    There are two workarounds for this issue:

    -- Set the PYTHONENCODING environment variable to UTF-8.

    -- Modify the fpgainfo script to force the use of UTF-8:

    • Add an import codecs statement at the top of the file with the
      other import statements.

    • Before the line that calls args.func(args), insert this comment and code line:

      # wrap stdout with the StreamWriter that does unicode sys.stdout = codecs.getwriter('UTF- 8')(sys.stdout)

  • When simulating the hello_intr_afu sample code, the
    af2cp_sTxPort.c1.hdr.rsvd2[5:4] has a value of X

    This issue will be resolved in the Intel Acceleration Stack 1.1
    version.

  • Partial reconfiguration with SR-IOV

    If using OPAE in a virtualized environment with SR-IOV enabled, we recommend disabling SR-IOV before performing partial reconfiguration. See "Partial Reconfiguration" in the "OPAE Intel FPGA Linux Device Driver Architecture" document for more information

  • fpgaAssignToInterface() and fpgaReleaseFromInterface() not supported

    The OPAE C API provides functions to assign individual AFCs to host interfaces (i.e. a virtual or physical function). Due to the internal implementation of fpga_token, these functions are not yet supported. Instead, we provide a simplified call fpgaAssignPortToInterface() that can assign a port by number to either the physical function (PF) or virtual function (VF). This function will eventually be replaced by the more generic implementation of fpgaAssignToInterface() and fpgaReleaseFromInterface() in a future release.

  • hssi_loopback tool help menu lists incorrect option for packet count

    The help menu indicates -p is the packet count, however the actual switch is -c.

  • AP6 condition may prevent clearing of port errors

    If the system encounters an AP6 condition (exceeded power or temperature threshold), it will report a port error. These errors can only be cleared (e.g. using fpgainfo) after the AP6 condition has been removed.

  • Driver may not display explicit incompatibility message if loaded on mismatched FIM version

    When trying to insert the Linux kernel driver modules while an FPGA platform with an unsupported FIM version is present in the system, the driver may fail to load and/or fail to print an explicit incompatibility warning message in the system log. Please make sure to use the driver only with a compatible FIM.

  • ASE: Multiple ModelSim simulator instances may crash when run on the same host

    When trying to run multiple instances of the ModelSim simulator on a single system, the simulator may crash. Only run one instance of ModelSim at the same time per system.

Assets 17