fpga: dfl-cxl-cache: depend on DRM

This resolves an undefined reference to drm_clflush_virt_range() when building a kernel without modules and minimal configuration. Signed-off-by: Peter Colberg <peter.colberg@intel.com>
OFS · Feb 1, 2024 · ba2f178 · ba2f178
1 parent 466c21c
commit ba2f178
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diff --git a/configs/dfl-config b/configs/dfl-config
@@ -61,6 +61,7 @@ CONFIG_PTP_DFL_TOD=m
 
 # CXL cache support
 
+CONFIG_DRM=m
 CONFIG_FPGA_DFL_CXL_CACHE=m
 
 # Test configs - not required for production environments

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
@@ -296,7 +296,7 @@ config FPGA_M10_BMC_SEC_UPDATE
 
 config FPGA_DFL_CXL_CACHE
 	tristate "Intel CXL cache driver"
-	depends on FPGA_DFL
+	depends on DRM && FPGA_DFL
 	help
 	  This is the driver for CXL cache Accelerated Function Unit
 	  (AFU) which provides interfaces to MMIO region and dma buffers.