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fpga: dfl: afu: update reset handling of Rev 2 of the Port feature #117

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fpgamatt
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@fpgamatt fpgamatt commented May 8, 2024

Revision 2 of the Device Feature List (DFL) Port can encompass more than one PCIe Physical Funtion. As such resetting the port must be handled differently. Disable actually resetting port for Rev 2 except for the Partial Reconfiguration flow.

Revision 2 of the Device Feature List (DFL) Port can encompass more
than one PCIe Physical Funtion. As such resetting the port must
be handled differently. Disable actually resetting port for Rev 2
except for the Partial Reconfiguration flow.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
@fpgamatt fpgamatt self-assigned this May 8, 2024
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@michael-adler michael-adler left a comment

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This has been working well for me for a few days. Running 2 AFUs in parallel no longer causes reset and reconfiguring PR has been ok.

@fpgamatt fpgamatt requested a review from pcolberg May 13, 2024 15:39
@fpgamatt fpgamatt merged commit 1c82071 into intel/fpga-ofs-dev-6.6-lts May 13, 2024
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@fpgamatt fpgamatt deleted the fpgamatt/fpga-ofs-dev-6.6-lts/more-port-reset branch May 13, 2024 16:10
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4 participants