AArch64: fix fmlal2 and fmlsl2 register offsets #6444
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ryanmkurtz
added
Feature: Processor/AARCH64
Status: Triage
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As part of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed an unexpected behaviour in the fmlal2 and fmlsl2 instructions for AARCH64. According to Section C7.2.124 and C7.2.128, the expected behaviour is to operate on the upper half of each operand register. While the current behaviour instead uses the upper bits for Rn, but the lower bits for Rm.