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RISC-V: Add WCH/QingKe XW extension #6390

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RISC-V: Add WCH/QingKe XW extension #6390

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9c37c35
RISC-V: Add WCH/QingKe XW extension
ArcaneNibble Apr 7, 2024
601f995
RISC-V: Update certification.manifest for QingKe XW
ArcaneNibble Apr 9, 2024
cd50f56
RISC-V: Fix copy-paste error in XW extension pcode
ArcaneNibble Apr 9, 2024
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4 changes: 4 additions & 0 deletions Ghidra/Processors/RISCV/certification.manifest
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Expand Up @@ -4,6 +4,7 @@ data/languages/RV32G.pspec||GHIDRA||||END|
data/languages/RV32GC.pspec||GHIDRA||||END|
data/languages/RV32I.pspec||GHIDRA||||END|
data/languages/RV32IC.pspec||GHIDRA||||END|
data/languages/RV32IMACFX.pspec||GHIDRA||||END|
data/languages/RV32IMC.pspec||GHIDRA||||END|
data/languages/RV64G.pspec||GHIDRA||||END|
data/languages/RV64GC.pspec||GHIDRA||||END|
Expand All @@ -14,6 +15,7 @@ data/languages/riscv.custom.sinc||GHIDRA||||END|
data/languages/riscv.ilp32d.slaspec||GHIDRA||||END|
data/languages/riscv.instr.sinc||GHIDRA||||END|
data/languages/riscv.ldefs||GHIDRA||||END|
data/languages/riscv.lp32qingke.slaspec||GHIDRA||||END|
data/languages/riscv.lp64d.slaspec||GHIDRA||||END|
data/languages/riscv.opinion||GHIDRA||||END|
data/languages/riscv.priv.sinc||GHIDRA||||END|
Expand All @@ -27,6 +29,7 @@ data/languages/riscv.rv32k.sinc||GHIDRA||||END|
data/languages/riscv.rv32m.sinc||GHIDRA||||END|
data/languages/riscv.rv32p.sinc||GHIDRA||||END|
data/languages/riscv.rv32q.sinc||GHIDRA||||END|
data/languages/riscv.rv32xw.sinc||GHIDRA||||END|
data/languages/riscv.rv64a.sinc||GHIDRA||||END|
data/languages/riscv.rv64b.sinc||GHIDRA||||END|
data/languages/riscv.rv64d.sinc||GHIDRA||||END|
Expand All @@ -41,6 +44,7 @@ data/languages/riscv.rvv.sinc||GHIDRA||||END|
data/languages/riscv.table.sinc||GHIDRA||||END|
data/languages/riscv.zi.sinc||GHIDRA||||END|
data/languages/riscv32-fp.cspec||GHIDRA||||END|
data/languages/riscv32-fp32.cspec||GHIDRA||||END|
data/languages/riscv32.cspec||GHIDRA||||END|
data/languages/riscv32.dwarf||GHIDRA||||END|
data/languages/riscv64-fp.cspec||GHIDRA||||END|
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16 changes: 16 additions & 0 deletions Ghidra/Processors/RISCV/data/languages/RV32IMACFX.pspec
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@@ -0,0 +1,16 @@
<?xml version="1.0" encoding="UTF-8"?>

<processor_spec>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="MXL" val="1"/>
<set name="RVA" val="1"/>
<set name="RVC" val="1"/>
<set name="RVF" val="1"/>
<set name="RVI" val="1"/>
<set name="RVM" val="1"/>
<set name="RVX" val="1"/>
</context_set>
</context_data>
</processor_spec>
13 changes: 13 additions & 0 deletions Ghidra/Processors/RISCV/data/languages/riscv.ldefs
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Expand Up @@ -128,6 +128,19 @@
<external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
<external_name tool="qemu" name="qemu-riscv32"/>
</language>
<language processor="RISCV"
endian="little"
size="32"
variant="RV32_QingKe"
version="1.3"
slafile="riscv.lp32qingke.sla"
processorspec="RV32IMACFX.pspec"
id="RISCV:LE:32:qingke">
<description>RISC-V 32 little WCH/QingKe</description>
<compiler name="gcc" spec="riscv32-fp32.cspec" id="gcc"/>
<external_name tool="gnu" name="riscv:rv32"/>
<external_name tool="DWARF.register.mapping.file" name="riscv32.dwarf"/>
</language>
<language processor="RISCV"
endian="little"
size="32"
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16 changes: 16 additions & 0 deletions Ghidra/Processors/RISCV/data/languages/riscv.lp32qingke.slaspec
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@@ -0,0 +1,16 @@
define endian=little;

@define XLEN 4
@define XLEN2 8
@define FLEN 4

@define MXLEN_1 31
@define MXLEN_2 30

@define ADDRSIZE "32"
@define FPSIZE "32"

@include "riscv.reg.sinc"
@include "riscv.table.sinc"
@include "riscv.instr.sinc"
@include "riscv.rv32xw.sinc"
1 change: 1 addition & 0 deletions Ghidra/Processors/RISCV/data/languages/riscv.reg.sinc
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Expand Up @@ -778,6 +778,7 @@ define token cinstr (16)
cfr0711=(7,11)
cop0712=(7,12)
cop0808=(8,8)
cop0810=(8,10)
cop0909=(9,9)
cop0910=(9,10)
cop0912=(9,12)
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63 changes: 63 additions & 0 deletions Ghidra/Processors/RISCV/data/languages/riscv.rv32xw.sinc
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@@ -0,0 +1,63 @@
# WCH / QingKe XW Extension

clbuimm: uimm is cop1212 & cop1011 & cop0506 [ uimm = (cop1212 << 0) | (cop1011 << 3) | (cop0506 << 1); ] { local tmp:$(XLEN) = uimm; export tmp; }
clhuimm: uimm is cop1012 & cop0506 [ uimm = (cop1012 << 3) | (cop0506 << 1); ] { local tmp:$(XLEN) = uimm; export tmp; }
clbuspimm: uimm is cop0710 [ uimm = (cop0710 << 0); ] { local tmp:$(XLEN) = uimm; export tmp; }
clhuspimm: uimm is cop0810 & cop0707 [ uimm = (cop0810 << 1) | (cop0707 << 4); ] { local tmp:$(XLEN) = uimm; export tmp; }


# c.lbu Ct,Ck(Cs)
:c.lbu cr0204s,clbuimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x1 & clbuimm
{
local ea:$(XLEN) = clbuimm + cr0709s;
cr0204s = zext(*[ram]:1 ea);
}

# c.sb Ct,Ck(Cs)
:c.sb cr0204s,clbuimm(cr0709s) is cr0709s & cr0204s & cop0001=0x0 & cop1315=0x5 & clbuimm
{
local ea:$(XLEN) = clbuimm + cr0709s;
*[ram]:1 ea = cr0204s:1;
}

# c.lhu Ct,Ck(Cs)
:c.lhu cr0204s,clhuimm(cr0709s) is cr0709s & cr0204s & cop0001=0x2 & cop1315=0x1 & clhuimm
{
local ea:$(XLEN) = clhuimm + cr0709s;
cr0204s = zext(*[ram]:2 ea);
}

# c.sh Ct,Ck(Cs)
:c.sh cr0204s,clhuimm(cr0709s) is cr0709s & cr0204s & cop0001=0x2 & cop1315=0x5 & clhuimm
{
local ea:$(XLEN) = clhuimm + cr0709s;
*[ram]:2 ea = cr0204s:2;
}

# c.lbusp Ct,Cm(Cc)
:c.lbusp cr0204s,clbuspimm(sp) is cr0204s & sp & cop0001=0x0 & cop0506=0x0 & cop1112=0x0 & cop1315=0x4 & clbuspimm
{
local ea:$(XLEN) = clbuspimm + sp;
cr0204s = zext(*[ram]:1 ea);
}

# c.sbsp Ct,Cm(Cc)
:c.sbsp cr0204s,clbuspimm(sp) is cr0204s & sp & cop0001=0x0 & cop0506=0x2 & cop1112=0x0 & cop1315=0x4 & clbuspimm
{
local ea:$(XLEN) = clbuspimm + sp;
*[ram]:1 ea = cr0204s:1;
}

# c.lhusp Ct,Cm(Cc)
:c.lhusp cr0204s,clhuspimm(sp) is cr0204s & sp & cop0001=0x0 & cop0506=0x1 & cop1112=0x0 & cop1315=0x4 & clhuspimm
{
local ea:$(XLEN) = clhuspimm + sp;
cr0204s = zext(*[ram]:2 ea);
}

# c.shsp Ct,Cm(Cc)
:c.shsp cr0204s,clhuspimm(sp) is cr0204s & sp & cop0001=0x0 & cop0506=0x3 & cop1112=0x0 & cop1315=0x4 & clhuspimm
{
local ea:$(XLEN) = clhuspimm + sp;
*[ram]:2 ea = cr0204s:2;
}
132 changes: 132 additions & 0 deletions Ghidra/Processors/RISCV/data/languages/riscv32-fp32.cspec
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@@ -0,0 +1,132 @@
<?xml version="1.0" encoding="UTF-8"?>

<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
<register name="gp"/>
<register name="tp"/>
</global>
<returnaddress>
<register name="ra"/>
</returnaddress>
<stackpointer register="sp" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="4">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a3"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a5"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a6"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a7"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa0"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa1"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa2"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa3"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa4"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa5"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa6"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="16" space="ram"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="a0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="a1"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa0"/>
</pentry>
<pentry minsize="4" maxsize="4">
<register name="fa1"/>
</pentry>
</output>
<unaffected>
<register name="sp"/>
<register name="gp"/>
<register name="tp"/>
<register name="s0"/>
<register name="s1"/>
<register name="s2"/>
<register name="s3"/>
<register name="s4"/>
<register name="s5"/>
<register name="s6"/>
<register name="s7"/>
<register name="s8"/>
<register name="s9"/>
<register name="s10"/>
<register name="s11"/>
<register name="fs0"/>
<register name="fs1"/>
<register name="fs2"/>
<register name="fs3"/>
<register name="fs4"/>
<register name="fs5"/>
<register name="fs6"/>
<register name="fs7"/>
<register name="fs8"/>
<register name="fs9"/>
<register name="fs10"/>
<register name="fs11"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>