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MahmouodMagdi/README.md

Hi there, I am Mahmoud Magdi 👋

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👨🏻‍💻 About Me

I am a passionate and extremely motivated Digital IC Design Engineer with interests in the field of Digital IC Design, Verification, ASIC Physical Implementation, and Computer Architecture.

With about 1 year of industry experience, my expertise lies in designing and verifying complex digital integrated circuits, ensuring their functionality, performance, and reliability.

I am dedicated to delivering innovative solutions and collaborating with cross-functional teams to bring ideas to life.

Continuous learning is not just a goal; it's a mindset that I bring to every project. I am regularly trusted to deliver on the toughest designs because I enjoy finding new approaches and I do not give up!

  • 🤔 My interests are with Digital IC Front-End Design, Verification, and ASIC Implementation
  • 💬 Ask me about anything, I am happy to help;
  • 📫 If you have a project, I'm available to help and also I'm looking for a new opportunities, you can always contact me.

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  1. Clock-Domain-Crossing-Synchronizers Clock-Domain-Crossing-Synchronizers Public

    Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…

    Verilog 37 3

  2. RTL-to-GDS-Implementaton-of-Low-Power-Configurable-Multi-Clock-Digital-System- RTL-to-GDS-Implementaton-of-Low-Power-Configurable-Multi-Clock-Digital-System- Public

    It is resposable of receiving commands through UART receiver to do different system functions as register file reading/writing or doing some processing using ALU block and send result as well as CR…

    Verilog

  3. Asynchronous-FIFO Asynchronous-FIFO Public

    A verilog implementation of an aynchronous FIFO (First In First Out).

    Verilog 2

  4. 256-bit-Modular-Adder-Subtractor 256-bit-Modular-Adder-Subtractor Public

    Hardware Implementation of a Modular Adder/Subtractor

    Verilog 1

  5. Memory-System-Verilog-Class-based-Testing-Environment Memory-System-Verilog-Class-based-Testing-Environment Public

    A SystemVerilog Class-Based Testing Environment to test 32*32 Memory Design

    SystemVerilog

  6. RTL-Design-of-ARM-based-AHB-to-APB-Bridge RTL-Design-of-ARM-based-AHB-to-APB-Bridge Public

    Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way

    SystemVerilog