Add variable to tcl scripts

Koheron · Jun 9, 2021 · 82b7326 · 82b7326
1 parent 78c1543
commit 82b7326
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Showing 3 changed files with 5 additions and 4 deletions.
diff --git a/examples/alpha250/phase-noise-analyzer/block_design.tcl b/examples/alpha250/phase-noise-analyzer/block_design.tcl
@@ -92,7 +92,7 @@ cell xilinx.com:ip:cic_compiler:4.0 cic {
   s_axis_data_tvalid [get_constant_pin 1 1]
 }
 
-set fir_coeffs [exec python $project_path/fir.py $n_stages $dec_rate $diff_delay print]
+set fir_coeffs [exec $python $project_path/fir.py $n_stages $dec_rate $diff_delay print]
 
 cell xilinx.com:ip:fir_compiler:7.2 fir {
   Filter_Type Decimation

diff --git a/fpga/fpga.mk b/fpga/fpga.mk
@@ -46,7 +46,7 @@ xpr: $(TMP_FPGA_PATH)/$(NAME).xpr
 
 $(TMP_FPGA_PATH)/$(NAME).xpr: $(CONFIG_TCL) $(XDC) $(PROJECT_PATH)/*.tcl $(CORES_COMPONENT_XML) | $(TMP_FPGA_PATH)
 	$(VIVADO_BATCH) -source $(FPGA_PATH)/vivado/project.tcl \
-	  -tclargs $(SDK_PATH) $(NAME) $(PROJECT_PATH) $(PART) $(BOARD_PATH) $(MODE) $(TMP_FPGA_PATH) $(TMP_FPGA_PATH)/xdc
+	  -tclargs $(SDK_PATH) $(NAME) $(PROJECT_PATH) $(PART) $(BOARD_PATH) $(MODE) $(TMP_FPGA_PATH) $(TMP_FPGA_PATH)/xdc $(PYTHON)
 	@echo [$@] OK
 
 .PHONY: fpga
@@ -64,7 +64,7 @@ $(TMP_FPGA_PATH)/$(NAME).hwdef: $(TMP_FPGA_PATH)/$(NAME).xpr | $(TMP_FPGA_PATH)
 .PHONY: block_design
 block_design: $(CONFIG_TCL) $(XDC) $(PROJECT_PATH)/*.tcl $(CORES_COMPONENT_XML)
 	$(VIVADO) -source $(FPGA_PATH)/vivado/block_design.tcl \
-	  -tclargs $(SDK_PATH) $(NAME) $(PROJECT_PATH) $(PART) $(BOARD_PATH) $(MODE) $(TMP_FPGA_PATH) $(TMP_FPGA_PATH)/xdc block_design_
+	  -tclargs $(SDK_PATH) $(NAME) $(PROJECT_PATH) $(PART) $(BOARD_PATH) $(MODE) $(TMP_FPGA_PATH) $(TMP_FPGA_PATH)/xdc $(PYTHON) block_design_
 
 # Open the Vivado project
 .PHONY: open_project

diff --git a/fpga/vivado/block_design.tcl b/fpga/vivado/block_design.tcl
@@ -6,7 +6,8 @@ set board_path [lindex $argv 4]
 set mode [lindex $argv 5]
 set output_path [lindex $argv 6]
 set xdc_filename [lindex $argv 7]
-set prefix [lindex $argv 8]
+set python [lindex $argv 8]
+set prefix [lindex $argv 9]
 
 # Add optional prefix to the project name
 if {$prefix == "block_design_"} {