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V0.20 (#516)
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* Increase plot range

* Add jobs to launch_runs from rsarwar87 bdc3680
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tvanderbruggen committed Mar 26, 2020
1 parent 93035ad commit 24d9686
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Showing 4 changed files with 7 additions and 5 deletions.
2 changes: 1 addition & 1 deletion examples/alpha250-4/adc-bram/test.py
Expand Up @@ -47,7 +47,7 @@
ax.set_ylabel('ADC Raw data')
ax.set_xlim((t_us[0], t_us[-1]))
# ax.set_ylim((-2**15, 2**15))
ax.set_ylim((-300, 300))
ax.set_ylim((-32768, 32768))
ax.legend(loc='upper right')
fig.canvas.draw()

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4 changes: 2 additions & 2 deletions fpga/fpga.mk
Expand Up @@ -53,11 +53,11 @@ $(TMP_FPGA_PATH)/$(NAME).xpr: $(CONFIG_TCL) $(XDC) $(PROJECT_PATH)/*.tcl $(CORES
fpga: $(BITSTREAM)

$(BITSTREAM): $(TMP_FPGA_PATH)/$(NAME).xpr | $(TMP_FPGA_PATH)
$(VIVADO_BATCH) -source $(FPGA_PATH)/vivado/bitstream.tcl -tclargs $< $@
$(VIVADO_BATCH) -source $(FPGA_PATH)/vivado/bitstream.tcl -tclargs $< $@ $(N_CPUS)
@echo [$@] OK

$(TMP_FPGA_PATH)/$(NAME).hwdef: $(TMP_FPGA_PATH)/$(NAME).xpr | $(TMP_FPGA_PATH)
$(VIVADO_BATCH) -source $(FPGA_PATH)/vivado/hwdef.tcl -tclargs $(TMP_FPGA_PATH)/$(NAME).xpr $(TMP_FPGA_PATH)/$(NAME).hwdef
$(VIVADO_BATCH) -source $(FPGA_PATH)/vivado/hwdef.tcl -tclargs $(TMP_FPGA_PATH)/$(NAME).xpr $(TMP_FPGA_PATH)/$(NAME).hwdef $(N_CPUS)
@echo [$@] OK

# Build the block design in Vivado GUI
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3 changes: 2 additions & 1 deletion fpga/vivado/bitstream.tcl
@@ -1,10 +1,11 @@
set xpr_filename [lindex $argv 0]
set bit_filename [lindex $argv 1]
set nCPU [lindex $argv 2]

open_project $xpr_filename

if {[get_property PROGRESS [get_runs impl_1]] != "100%"} {
launch_runs impl_1 -to_step route_design
launch_runs impl_1 -to_step route_design -jobs $nCPU
wait_on_run impl_1
}

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3 changes: 2 additions & 1 deletion fpga/vivado/hwdef.tcl
@@ -1,10 +1,11 @@
set xpr_filename [lindex $argv 0]
set hwdef_filename [lindex $argv 1]
set nCPU [lindex $argv 2]

open_project $xpr_filename

if {[get_property PROGRESS [get_runs synth_1]] != "100%"} {
launch_runs synth_1
launch_runs synth_1 -jobs $nCPU
wait_on_run synth_1
}

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