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PipelineC-Graphics

Graphics demos implemented using PipelineC.

This primarily consists of a ray tracing demo created using CflexHDL C++ code.

Work contained in these repositories is experimental and in active development. Please report any issues that are encountered.

Sphery vs. Shapes:

A fully working interactive raytraced game written in C and translated to a circuit. No CPU is used, and the few resources used run at an outstanding power efficiency. Check out a demo video of gameplay on real hardware! image

A detailed article describing this work is here

Install

  • Install clang 14
    wget https://apt.llvm.org/llvm.sh
    chmod +x llvm.sh
    sudo ./llvm.sh 14
    # Copy/link specific .so file to generic .so to avoid missing .so file error
    sudo cp /usr/lib/x86_64-linux-gnu/libclang-14.so.14.0.6 /usr/lib/x86_64-linux-gnu/libclang-14.so
    
  • Install sdl2 lib, OpenMP, Un-If-Def Tool
    sudo apt install libsdl2-dev
    sudo apt install libomp-dev
    sudo apt install unifdef
    
  • Clone repos adjacent to each other in one dir
    git clone https://github.com/JulianKemmerer/PipelineC-Graphics
    git clone https://github.com/suarezvictor/CflexHDL
    git clone https://github.com/JulianKemmerer/PipelineC
    
  • Install open source EDA tools
    export PATH="<extracted_location>/oss-cad-suite/bin:$PATH"
    
  • Make CFlexHDL cflexparser
    cd CflexHDL/cflexparser
    make
    # may need to add '-fno-lto' to makefile to avoid
    #   fatal error: bytecode stream in file libpython3.8.a generated with LTO version 6.0 instead of the expected 8.1
    
  • Install Litex
    • TODO more info...

Building

Boards supported are the Digilent Arty-100T and the OrangeCrab 85F v0.2.

For the Arty: make clean BOARD=digilent_arty FRAME_WIDTH=1920 FRAME_HEIGHT=1080 load
For the OrangeCrab: make clean BOARD=gsd_orangecrab load (default 640x480 resolution, uses open source toolchain for synthesis)
You need to select DVI=True or DVI=False in litex_soc.py to output digital video or analog video with a VGA PMOD

Full pipelining can take some hours, for faster processing you can try simulation options like make sim, make gen, or make verilator

Contact

Social Media: @pipelinec_hdl @suarezvictor

Talk on Discord:

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