This project demonstrates the datapath design in software for the MIPS instruction set. MIPS is an acronym for Microprocessor without Interlocked Pipeline Stages. It is a popular computer architecture that is used in embedded processors. This design is for a 32-bit single-cycle processor using the Xilinx ISE Design Suite 14.6.
The processor architecture has five stages: Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory Access (MA), Write Back (WB).
IF Stage - The instruction is fetched from memory using the Program Counter (PC) register and stored in Instruction Register.
ID Stage - The instruction bits in the Instruction Register are decoded and next PC is calculated. Operands are read from the Register File and branching conditions are tested if the instruction is a branch type instruction.
EX Stage - The instruction is executed. If the instruction is an arithmetic or logical operation, the results are computed by the Arithmetic Logic Unit (ALU). If it is a load or store word instruction, the approprate addresses are computed by the ALU.
MA Stage - Any memory access that is required by the current instruction is performed. For load word instructions, an operand is loaded from memory. For store words, the operand is stored into memory.
WB Stage - The operation results are written back to the destination register in the Register File.
The 32-bit Instruction Formats for the Register, Immediate, and Jump instruction types are shown below.
The Instruction Memory has the following instructions.
Schem.sch contains the top-level schematic file for this design. The testbench for this schematic file is included in the project design. This design can be optimized by using a pipelined datapath to improve throughput and execute multiple instructions per cycle.
Selected Device : 3s100ecp132-5
Number of Slices: 507 out of 960 52%
Number of Slice Flip Flops: 23 out of 1920 1%
Number of 4 input LUTs: 1066 out of 1920 55%
Number used as logic: 746
Number used as RAMs: 320
Number of IOs: 24
Number of bonded IOBs: 24 out of 83 28%
Number of GCLKs: 2 out of 24 8%