UHD 4.6.0.0
The UHD 4.6.0.0 release adds:
- Phase repeatability, dual rate support, and lower sampling rates for the NI Ettus USRP X440.
Changelog:
- ci
- only build docker images once per week
- propagate testLength to RF ATS
- replace deprecated ruamel.yaml methods
- use build farm for windows builds
- cmake
- Fix make_x410 and make_x440 targets
- deb
- copyright file update to eliminate errors and warnings
- docs
- X440: Add FBX to daughterboard list
- X440: Corrected web link syntax in FBX doc.
- X440: Add X440_X4_200 to image flavors
- X440: Add dual-rate documentation
- examples
- L band capture example using dual rate
- fpga
- ci: Add X440_X4_200 to pipelines
- lib: Allow buffering in eth_ipv4_chdr_adapter
- n3xx: Add CE clock
- rfnoc: Add clock info to backend ifc
- rfnoc: radio: Add clock index parameters
- tools: Add X440_X4_200 to X440 package
- x400: Add CE clock
- x400: Add X440 200 MHz variant with DDC/DUC
- x400: Split DRAM interface into two banks
- x400: Update PL DRAM speed bin
- x400: bump minor revision
- x400: pps_sync cleanup
- x400: propagate pps_sync changes
- x400: update signals to run on two domains
- x440: cpld: led control cleanup
- x440: remove extra synchronizer
- images
- bump x4xx fpga images
- update non-x4xx images
- lib
- rfnoc: Add clock info fields to client zero
- rfnoc: Add support for auto-clock discovery
- x4xx: Use auto clock ID in x400_radio_control
- mpm
- x440: Add lookup table for default MCR per DSP bandwidth
- x440: Multi-Tile Sync disabled when using dual rate
- x400: Align FPGA revision
- x400: match HDL PPS updates
- x400: make PRC a multiple of both rfdc rates
- fix timekeeper misalignment
- multi_usrp
- Added module_serial to info
- rfnoc
- Enable SEP throttle register
- image builder: Add clock index support to image builder
- utils
- init device with gpsdo sources in query_gpsdo_sensors
- x4xx
- Add support for auto clock ID
- FPGA designs now use a replay block per utilized DRAM bank
- x440
- Add support for using radio block specific master clock rates
- X4_440 and X4_1600 fpga image now contain 2 replay blocks
(number of ports per replay block halved compared to previous release)