Skip to content

EagleStephen/FIFO-VHDL-Simple-Code-

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

8 Commits
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Test Bench simulation on Modelsim 10.5c

Simulation with DEPTH 4

Fifo_Tx

On the testbench file the data trame is 34 bits long. You need to manually modify the size of the Fifo or else you can add variables such as Width and Depth.

If you are importing into a main design, don't forget to add the component and declare the port map.

Simulation with DEPTH 34

image

Click on the images to open in new tab

About

Simple Fifo in VHDL

Topics

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published

Languages