i#6662 public traces, part 3: regdeps disasm #6799
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regdeps instructions.
Spacing is important there, cannot be changed.
stay within 90 chars lines.
modifying it for all arches.
edeiana
commented
May 8, 2024
edeiana
commented
May 8, 2024
|
There are 2 tests consistently failing in ci-x86 / x86-64: EDIT: this has been fixed. |
encodings have at least a 4 byte header and are 4 byte aligned, so let's take advantage of that.
Does this test run in arm and riscv?
edeiana
changed the title
edeiana
commented
May 16, 2024
derekbruening
approved these changes
May 16, 2024
For ARM this test fails because of "/lib/ld-linux-armhf.so.3: No such file or directory". Added FIXME comment about it.
edeiana
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May 17, 2024
Modifies the view tool to handle OFFLINE_FILE_TYPE_ARCH_REGDEPS traces, leveraging the disassembly of DR_ISA_REGDEPS instructions. When visualizing DR_ISA_REGDEPS instructions, the view tool still prints the instruction length and PC, which for OFFLINE_FILE_TYPE_ARCH_REGDEPS traces are the same as those in the original trace. Then, after the PC, the instruction encoding, categories, operation size, and registers are printed following the disassembly format of DR_ISA_REGDEPS instructions (xref: #6799). DR_ISA_REGDEPS instructions printed by the view tool look as follows: ``` [...] ifetch 10 byte(s) @ 0x00007f86ef03d107 00001931 04020204 load store [4byte] %rv0 %rv2 %rv36 -> %rv0 [...] 00000026 ``` We also fix a formatting bug in DR_ISA_REGDEPS instruction disassembly, where we were missing a new line when the instruction encoding spills into a second line. Issue: #6662
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Adds disassembling for DR_ISA_REGDEPS instructions.
Specifically, when we disassemble DR_ISA_REGDEPS instructions, we print the
instruction encoding (divided in 4 byte words, can span one or two lines, similar to x86),
we substitute the opcode with categories, we print the operations size (e.g.,
[4byte]),and then the source and destination virtual register names (e.g.,
%rv3).Disassembled instructions look as follows:
00000812 06260606 load [8byte] %rv4 -> %rv4 %rv36In general, they follow this pattern:
[encoding (in 4 byte words)] [categories] [operation_size] [src_regs -> dst_regs]
Issue: #6662