GitHub - DavidKopalaCU/Verilog-ReactionTimer: A Reaction Timer for the DE10 Lite FPGA Written in Verilog HDL

DavidKopalaCU / Verilog-ReactionTimer Public

A Reaction Timer for the DE10 Lite FPGA Written in Verilog HDL

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Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
.qsys_edit		.qsys_edit
.gitignore		.gitignore
DE10_LITE_Reaction_Timer.cdf		DE10_LITE_Reaction_Timer.cdf
DE10_LITE_Reaction_Timer.htm		DE10_LITE_Reaction_Timer.htm
DE10_LITE_Reaction_Timer.qpf		DE10_LITE_Reaction_Timer.qpf
DE10_LITE_Reaction_Timer.qsf		DE10_LITE_Reaction_Timer.qsf
DE10_LITE_Reaction_Timer.sdc		DE10_LITE_Reaction_Timer.sdc
DE10_LITE_Reaction_Timer.sld		DE10_LITE_Reaction_Timer.sld
DE10_LITE_Reaction_Timer.v		DE10_LITE_Reaction_Timer.v
DE10_LITE_Reaction_Timer_assignment_defaults.qdf		DE10_LITE_Reaction_Timer_assignment_defaults.qdf
Project2_top.v		Project2_top.v
bcd_counter.v		bcd_counter.v
bcd_decoder.v		bcd_decoder.v
clock_divider.v		clock_divider.v
default_state.v		default_state.v
finite_state_machine.v		finite_state_machine.v
high_score_state.v		high_score_state.v
lfsr.v		lfsr.v
lfsr_nine.v		lfsr_nine.v
score_display_state.v		score_display_state.v
simple_machine.v		simple_machine.v
simple_machine_2.v		simple_machine_2.v
simple_machine_3.v		simple_machine_3.v
three_to_eight_decoder.v		three_to_eight_decoder.v
timing_state.v		timing_state.v
waiting_state.v		waiting_state.v