Processor

Image processor using Altera DE FPGA

Includes

Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
Resources		Resources
db		db
greybox_tmp		greybox_tmp
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
ALU.v		ALU.v
ALU.v.bak		ALU.v.bak
CONTROL_UNIT.v		CONTROL_UNIT.v
CONTROL_UNIT.v.bak		CONTROL_UNIT.v.bak
CPU.v		CPU.v
CPU.v.bak		CPU.v.bak
IMAGE.mif		IMAGE.mif
IMAGE_RAM.bsf		IMAGE_RAM.bsf
IMAGE_RAM.cmp		IMAGE_RAM.cmp
IMAGE_RAM.inc		IMAGE_RAM.inc
IMAGE_RAM.qip		IMAGE_RAM.qip
IMAGE_RAM.v		IMAGE_RAM.v
IMAGE_RAM_bb.v		IMAGE_RAM_bb.v
IMAGE_RAM_inst.v		IMAGE_RAM_inst.v
INSTRUCTION_FILE-for.mif		INSTRUCTION_FILE-for.mif
INSTRUCTION_FILE.mif		INSTRUCTION_FILE.mif
INSTRUCTION_ROM.bsf		INSTRUCTION_ROM.bsf
INSTRUCTION_ROM.cmp		INSTRUCTION_ROM.cmp
INSTRUCTION_ROM.inc		INSTRUCTION_ROM.inc
INSTRUCTION_ROM.qip		INSTRUCTION_ROM.qip
INSTRUCTION_ROM.v		INSTRUCTION_ROM.v
INSTRUCTION_ROM.v.bak		INSTRUCTION_ROM.v.bak
INSTRUCTION_ROM_bb.v		INSTRUCTION_ROM_bb.v
INSTRUCTION_ROM_inst.v		INSTRUCTION_ROM_inst.v
MUX_FOR_BUS_B.v		MUX_FOR_BUS_B.v
MUX_FOR_BUS_B.v.bak		MUX_FOR_BUS_B.v.bak
PROCESSOR.v		PROCESSOR.v
PROCESSOR.v.bak		PROCESSOR.v.bak
Processo.sdc		Processo.sdc
Processor.out.sdc		Processor.out.sdc
Processor.qpf		Processor.qpf
Processor.qsf		Processor.qsf
Processor.qws		Processor.qws
Processor_nativelink_simulation.rpt		Processor_nativelink_simulation.rpt
RAM.bsf		RAM.bsf
RAM.cmp		RAM.cmp
RAM.inc		RAM.inc
RAM.qip		RAM.qip
RAM.v		RAM.v
RAM.v.bak		RAM.v.bak
RAM_bb.v		RAM_bb.v
RAM_inst.v		RAM_inst.v
README.md		README.md
REGISTER.v		REGISTER.v