Name		Name	Last commit message	Last commit date
Latest commit History 75 Commits
AXI_SpaceWire_IP_1.0		AXI_SpaceWire_IP_1.0
doc		doc
edit_AXI_SpaceWire_IP_v1_0.cache		edit_AXI_SpaceWire_IP_v1_0.cache
edit_AXI_SpaceWire_IP_v1_0.hw		edit_AXI_SpaceWire_IP_v1_0.hw
edit_AXI_SpaceWire_IP_v1_0.ip_user_files		edit_AXI_SpaceWire_IP_v1_0.ip_user_files
edit_AXI_SpaceWire_IP_v1_0.sim/sim_1/behav/xsim		edit_AXI_SpaceWire_IP_v1_0.sim/sim_1/behav/xsim
edit_AXI_SpaceWire_IP_v1_0.srcs		edit_AXI_SpaceWire_IP_v1_0.srcs
LICENCE		LICENCE
README.md		README.md
edit_AXI_SpaceWire_IP_v1_0.xpr		edit_AXI_SpaceWire_IP_v1_0.xpr
fifointerface_rx_tb_behav_rx.wcfg		fifointerface_rx_tb_behav_rx.wcfg
fifointerface_tx_tb_behav.wcfg		fifointerface_tx_tb_behav.wcfg
fifointerface_tx_tb_behav_test.wcfg		fifointerface_tx_tb_behav_test.wcfg

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AXI_SpaceWire_IP

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Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).

arm zynq xilinx spacewire soc axi

GPL-3.0 license

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