v5.0 Five Stage Pipelined Architecture

The core is now converted from FSM based implementation to a full 5 stage pipelined architecture.

New

• Added clock enables for pipeline control of each stage
• Added pipeline control logic on rv32i_core.v which includes detection and elimination of branch and data hazards
• Added returned instructions minstret and clk cycle count mcycle status on the output display of rv32i_soc_TB and test.sh for easier evaluation of pipeline efficiency
• rv32i_fetch.v = retrieves instruction from the memory [FETCH STAGE]

Pipeline Features

• 5 pipelined stages
• Separate data and instruction memory interface [Harvard architecture]
• Load instructions take a minimum of 2 clk cycles
• Taken branch and jump instructions take a minimum of 6 clk cycles [No Branch Prediction Used]
• Two consecutive instructions with data dependency take a minimum of 2 clk cycles. Nonconsecutive instructions with data dependency take a minimum of 1 clk cycle [Operation Forwarding used]
• All remaining instructions take a minimum of 1 clk cycle

v4.1 After Second Design Review

Fix

• Moved assembly testfiles (extra/) and all test scripts (test.sh, sections.py, wave.do) to a single folder /test. This makes the repository more orderly
• Moved the rv32i_soc_TB.v from rtl/ to test/ to separate testbench from the synthesizable verilog files
• Script will now first check if riscv-tests/ exists. If not, clone the repository from here. This ensures latest updates on riscv-tests will be integrated on the regression tests
• Added i_ and o_ prefixes for all input and output pins for an easier distinction of pin connections

v4.0 RISC-V Compliant

rv32ui (RV32 User-Mode Integer-Only) and rv32mi (RV32 Machine-Mode Integer-Only) testfiles from RISC-V International are now part of the regression tests. All tests passed.

Fix

• Instruction address misaligned exception is now thrown at the taken branch or jump instruction (previous implementation throws an exception after jumping or branching to the misaligned instruction address). Decoding logic for is_inst_addr_misaligned is now moved from rv32i_decoder to rv32i_csr since the ALU [EXECUTE STAGE] must first compute the address to know if address is misaligned.
• Instruction memory and Data memory are now merged into one regfile. This is to pass fence_i.S tesfile. The interface for instruction and data are still separate.

New

• riscv-tests/ folder = contains the RISC-V International RV32I tests
• riscv-test-env/ folder = contains the test environment necessary for running the RISCV International RV32I tests
• extra/ folder = this is the previous folder named testbank which contains my own assembly testfiles

v3.0 Zicsr Extension Support

The core now supports Zicsr extension.

Fix

• Added more debug information to display on the rv32i_soc_TB output
• Set default_nettype of all modules to none

New

• rv32i_csr.v = Zicsr extension module
• csr_op.s, exceptions.s, instret.s, and interrupts.s = assembly testfiles for Zicsr extension

Supported Features of Zicsr Extension Module

• CSR instructions: CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI
• Interrupts: External Interrupt, Timer Interrupt, Software Interrupt
• Exceptions: Illegal Instruction, Instruction Address Misaligned, Ecall, Ebreak, Load/Store Address Misaligned
• All relevant machine level CSRs

v2.0 Automated Testbench

The testbench is now automated and more exhaustive by using assembly files as the testcases. Multiple bugs were discovered by the automated testbench and is now fixed.

Fix

• Casted operator a to $signed() for SRA(shift right arithmetic) operation of ALU
• Added logic for choosing which byte/halfword to be loaded to basereg in LB(load byte) and LH(load halfword) instruction
• Converted reg sum to wire in rv32i_writeback since it's always equating to zero due to the blocking assignment
• Initialized all basereg to zero to avoid error in testbench (e.g. addi instruction loads value to 12 LSBs but since the 24 MSBs are still X(unknown) when basereg is not initialized, the ALU operation fails)

New

• test.sh = shell script for automating the testbench
• sections.py = python script used by test.sh to extract the text and data sections from the binary file output of the compiler
• testbank/ = assembly testfiles for all 37 basic instructions with RISC-V International's riscv-tests pass/fail criteria

v1.1 After Design Review

Fix

• Replaced all tabs with spaces for better alignment
• Registered all outputs of modules to reduce long timing paths
• Removed cross-referencing of parameters by using single-bit decoding
• Removed basereg initialization to zero (spec does not require basereg, except x0, to be initialized to zero)
• Wrapped up FSM to its own module: rv32i_fsm
• Solved warnings from Modelsim simulation

New

• scripts for automatic simulation with Modelsim and Vivado

v1.0 First Working Implementation

My first working implementation of RV32 Integer core.This is FSM based (no pipelining) and no CSR yet. A simple testbench (executes a hexfile for instruction) is used to verify the core.