This repository builds upon the work of RV32I_Single_Cycle_CPU by extending the RISC-V Data Path to support a 5-Stage Pipelined CPU architecture. It simplifies the RV32I Single Cycle CPU and enhances it into a more efficient pipelined design.
Ammar-Bin-Amir/RV32I_5-Stage_Pipelined_CPU
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
Processor Design of RV32I 5-Stage Pipelined CPU
Topics
Resources
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published